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Task #4907

closed

[verilog][translator] Добавить в проект Verilog-транслятор

Added by Alexander Kamkin over 10 years ago. Updated over 10 years ago.

Status:
Closed
Priority:
High
Assignee:
Alexander Kamkin
Category:
-
Target version:
0.1
Start date:
05/07/2014
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Published in build:

Description

  1. Добавить veritrans.jar.
  2. Сделать обертку VerilogParser extends Parser.
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