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Feature #9990
closedcheck for variable/net redeclarations
Start date:
12/17/2019
Due date:
% Done:
50%
Estimated time:
Published in build:
0.1.3-beta-201002
Description
As it is specified in IEEE-1364-2005 Standard for Verilog Hardware Description Language,
It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
So the tool should detect erroneous redeclarations.
For more details see 4.2.1 and 4.2.2 chapters.
Updated by Sergey Smolov over 4 years ago
- Status changed from New to Feedback
- Assignee changed from Alexander Kamkin to Alexey Danilov
- Priority changed from Normal to High
Alexey, could you implement this small feature? It is relevant to your work at VeriTrans.
Updated by Alexey Danilov over 4 years ago
- Status changed from Feedback to Resolved
Updated by Sergey Smolov over 4 years ago
- Status changed from Resolved to Verified
Updated by Sergey Smolov about 4 years ago
- Status changed from Verified to Closed
Updated by Sergey Smolov about 4 years ago
- Published in build set to 0.1.3-beta-201002
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