Overview
Verilog Translator (VeriTrans) is an ANTLR-based Verilog front-end in couple with some back-ends.
Licensing and Distribution¶
The VeriTrans package is distributed under the Apache License, Version 2.0, which implies the freedom to use the software for any purpose (to distribute it, to modify it and to distribute modified versions of the software) under the terms of the license, but requires preservation of the copyright notice and disclaimer.
The package can be downloaded from the Files page.
Latest news
Verilog Translator 0.1.3 released
Verilog Translator 0.1.3 has been released
Verilog Translator 0.1.2 released
Verilog Translator 0.1.2 has been released.
Verilog Translator 0.1.1 released.
We are happy to announce the first release of the Verilog Translator tool.
Members
Manager: Alexander Kamkin, Sergey Smolov
Developer: Alexander Kamkin, Mikhail Chupilko, Mikhail Lebedev, Sergey Smolov
Reporter: Maksim Jenihhin
Project Creator: Alexander Kamkin