Found Errors¶

1.
src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer1 -> RDealer1
src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer2 -> RDealer2

2.

--- a/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v
+++ b/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v
@@ -14,7 +14,7 @@ module Control(
         SESel,

         Reset,
-        Clk ,
+        Clk// ,
               );
    reg monitor_lw;
    reg monitor_j;