Found Errors » History » Revision 3
Revision 2 (Sergey Smolov, 06/29/2018 05:22 PM) → Revision 3/5 (Sergey Smolov, 08/09/2018 02:38 PM)
h1. Found Errors 1. src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer1 -> RDealer1 src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer2 -> RDealer2 2. <pre><code class="diff"> --- a/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v +++ b/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v @@ -14,7 +14,7 @@ module Control( SESel, Reset, - Clk , + Clk// , ); reg monitor_lw; reg monitor_j; </code></pre>