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Found Errors » History » Revision 2

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Sergey Smolov, 06/29/2018 05:22 PM


Found Errors

src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer1 -> RDealer1
src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer2 -> RDealer2

Updated by Sergey Smolov over 6 years ago · 5 revisions