RISC-V Instruction Set » History » Revision 6
Revision 5 (Alexander Protsenko, 11/04/2016 02:50 PM) → Revision 6/50 (Andrei Tatarnikov, 05/09/2018 04:24 PM)
h1. RISC-V Instruction Set
{font-weight:bold; background:#ddd}. |/2. *Category* |\2. *RISC-V (Version 2.2)* 2.1)* |\2. *MicroTESK* |
{background:#dde}. | *Instructions* | *Amount* | *Instructions* | *Amount* |
{background:#fcc}. | Arithmetic Logic Unit | ADDI
SLTI
SLTIU
XLEN
ANDI
ORI
XORI
SRLI
SLLI
LUI
AUIPC
ADD
SUB
SLT
SLTU
AND
OR
XOR
SLL
SRL
SRA | 21+ | | 0+ |
{background:#fcc}. | Branch| JAL
JALR
BEQ
BNE
BLT
BLTU
BGE
BGEU
BGT
BGTU
BLE
BLEU
BLT
BLTU
BGE
BGEU | 16 | | 0+ |
{background:#ff9}. | Memory Access | LW
LH
LHU
LB
LBU
SW
SH
SB | 8 | | 0 |
{background:#fcc}. | System | CSRRW
CSRRS
CSRRC
CSRRWI
CSRRSI
CSRRCI
RDCYCLE
RDTIME
RDINSTRET | 9 | | 0 |
{background:#cfc}. | Other | NOP | 1 | NOP | 1 |
{background:#ddd}. | Total: || 65 | | 1+ |
{background:#cfc}. |100%|
{background:#ff9}. |50+%|
{background:#fcc}. |0+%|