RISC-V Instruction Set » History » Version 4
Alexander Protsenko, 11/04/2016 02:13 PM
| 1 | 1 | Alexander Protsenko | h1. RISC-V Instruction Set |
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| 3 | 2 | Alexander Protsenko | {font-weight:bold; background:#ddd}. |/2. *Category* |\2. *RISC-V (Version 2.1)* |\2. *MicroTESK* | |
| 4 | {background:#dde}. | *Instructions* | *Amount* | *Instructions* | *Amount* | |
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| 5 | {background:#fcc}. | Arithmetic Logic Unit | ADDI |
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| 6 | SLTI |
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| 7 | SLTIU |
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| 8 | XLEN |
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| 9 | ANDI |
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| 10 | ORI |
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| 11 | XORI |
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| 12 | SRLI |
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| 13 | SLLI |
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| 14 | LUI |
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| 15 | AUIPC |
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| 16 | ADD |
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| 17 | SUB |
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| 18 | SLT |
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| 19 | SLTU |
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| 20 | AND |
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| 21 | OR |
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| 22 | XOR |
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| 23 | SLL |
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| 24 | SRL |
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| 25 | SRA | 21+ | | 0+ | |
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| 26 | 3 | Alexander Protsenko | {background:#fcc}. | Branch| JAL |
| 27 | JALR |
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| 28 | BEQ |
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| 29 | BNE |
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| 30 | BLT |
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| 31 | BLTU |
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| 32 | BGE |
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| 33 | BGEU |
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| 34 | BGT |
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| 35 | BGTU |
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| 36 | BLE |
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| 37 | BLEU |
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| 38 | BLT |
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| 39 | BLTU |
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| 40 | BGE |
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| 41 | 4 | Alexander Protsenko | BGEU | 16 | | 0+ | |
| 42 | {background:#ff9}. | Memory Access | LW |
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| 43 | LH |
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| 44 | LHU |
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| 45 | LB |
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| 46 | LBU |
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| 47 | SW |
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| 48 | SH |
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| 49 | SB | 8 | | 0 | |
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| 50 | {background:#fcc}. | System | CSRRW |
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| 51 | CSRRS |
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| 52 | CSRRC |
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| 53 | CSRRWI |
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| 54 | CSRRSI |
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| 55 | CSRRCI |
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| 56 | RDCYCLE |
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| 57 | RDTIME |
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| 58 | RDINSTRET | 9 | | 0 | |
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| 59 | 2 | Alexander Protsenko | {background:#cfc}. | Other | NOP | 1 | NOP | 1 | |
| 60 | 4 | Alexander Protsenko | {background:#ddd}. | Total: || 50+ | | 1+ | |
| 61 | 1 | Alexander Protsenko | |
| 62 | {background:#cfc}. |100%| |
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| 63 | {background:#ff9}. |50+%| |
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| 64 | {background:#fcc}. |0+%| |