RISC-V Instruction Set » History » Revision 18
Revision 17 (Andrei Tatarnikov, 07/26/2018 02:54 PM) → Revision 18/50 (Andrei Tatarnikov, 07/26/2018 02:59 PM)
h1. RISC-V Instruction Set
{font-weight:bold; background:#ddd}. |/2. *Category* |\2. *RISC-V (Version 2.2)* |\2. *MicroTESK* |
{background:#dde}. | *Instructions* | *Amount* | *Instructions* | *Amount* |
{background:#fcc}. | Arithmetic Logic Unit | ADDI
SLTI
SLTIU
XLEN
ANDI
ORI
XORI
SRLI
SLLI
LUI
AUIPC
ADD
SUB
SLT
SLTU
AND
OR
XOR
SLL
SRL
SRA | 21+ | | 0+ |
{background:#fcc}. | Branch| JAL
JALR
BEQ
BNE
BLT
BLTU
BGE
BGEU
BGT
BGTU
BLE
BLEU
BLT
BLTU
BGE
BGEU | 16 | | 0+ |
{background:#ff9}. | Memory Access | LW
LH
LHU
LB
LBU
SW
SH
SB | 8 | | 0 |
{background:#fcc}. | System | CSRRW
CSRRS
CSRRC
CSRRWI
CSRRSI
CSRRCI
RDCYCLE
RDTIME
RDINSTRET | 9 | | 0 |
{background:#cfc}. | Other | NOP | 1 | NOP | 1 |
{background:#ddd}. | Total: || 65 | | 1+ |
{background:#cfc}. |100%|
{background:#ff9}. |50+%|
{background:#fcc}. |0+%|
h1. Instructions supported by MicroTESK for RISC-V
{font-weight:bold; background:#ddd}. | Instruction Set | Instructions | Specified | Validated |
| RV32I | | ? | ? |
| RV64I | | ? | ? |
{background:#cfc}. | *RV32M* | MUL
MULH
MULHSU
MULHU
DIV
DIVU
REM
REMU | Yes (8/8) | Yes (8/8) |
{background:#cfc}. | *RV64M* | MULW
DIVW
DIVUW
REMW
REMUW | Yes (5/5) | Yes (5/5) |
{background:#cfc}. | *RV32A* | LR.W
SC.W
AMOSWAP.W
AMOADD.W
AMOXOR.W
AMOAND.W
AMOOR.W
AMOMIN.W
AMOMAX.W
AMOMINU.W
AMOMAXU.W | Yes (11/11) | Yes (11/11) |
{background:#cfc}. | *RV64A* | LR.D
SC.D
AMOSWAP.D
AMOADD.D
AMOXOR.D
AMOAND.D
AMOOR.D
AMOMIN.D
AMOMAX.D
AMOMINU.D
AMOMAXU.D | Yes (11/11) | Yes (11/11) |
{background:#ff9}. | *RV32F* | FLW
FSW
FMADD.S
FMSUB.S
FNMSUB.S
FNMADD.S
FADD.S
FSUB.S
FMUL.S
FDIV.S
FSQRT.S
FSGNJ.S
FSGNJN.S
FSGNJX.S
FMIN.S
FMAX.S
FCVT.W.S
FCVT.WU.S
FMV.X.W (FMV.X.S)
FEQ.S
FLT.S
FLE.S
FCLASS.S
FCVT.S.W
FCVT.S.WU
FMV.W.X (FMV.S.X) | Yes (26/26) | Partially (?/26) |
{background:#ff9}. | *RV64F* | FCVT.L.S
FCVT.LU.S
FCVT.S.L
FCVT.S.LU | Yes (4/4) | Partially (?/4) |
{background:#ff9}. | *RV32D* | FLD
FSD
FMADD.D
FMSUB.D
FNMSUB.D
FNMADD.D
FADD.D
FSUB.D
FMUL.D
FDIV.D
FSQRT.D
FSGNJ.D
FSGNJN.D
FSGNJX.D
FMIN.D
FMAX.D
FCVT.S.D
FCVT.D.S
FEQ.D
FLT.D
FLE.D
FCLASS.D
FCVT.W.D
FCVT.WU.D
FCVT.D.W
FCVT.D.WU | Yes (26/26) | Partially Yes (?/26) |
{background:#ff9}. | *RV64D* RV64D | FCVT.L.D
FCVT.LU.D
FMV.X.D
FCVT.D.L
FCVT.D.LU
FMV.D.X | 6 | Yes (6/6) | Partially (?/26) No |
{background:#ddd}. | Total | | | |
{background:#cfc}. | Fully supported |
{background:#ff9}. | Partially supported |
{background:#fcc}. | Unsupported |