MicroTESK

revisions.xml

<revisions>
 <revision name="MEM_SV32"/>
 <revision name="MEM_SV64">
  <includes name="MEM_SV39"/>
  <includes name="MEM_SV48"/>
 </revision>

 <revision name="RV32I">
  <includes name="MEM_SV32"/>
 </revision>
 <revision name="RV32C"/>
 <revision name="RV32FC"/>
 <revision name="RV64C"/>
 <revision name="RV64I">
  <includes name="RV32I"/>
  <excludes name="MEM_SV32"/>
  <includes name="MEM_SV64"/>
 </revision>
 <revision name="RV32M">
  <includes name="RV32I"/>
 </revision>
 <revision name="RV64M">
  <includes name="RV32M"/>
  <includes name="RV64I"/>
 </revision>
 <revision name="RV32A"/>
 <revision name="RV64A">
  <includes name="RV32A"/>
  <includes name="RV64I"/>
 </revision>
 <revision name="RV32F"/>
 <revision name="RV64F">
  <includes name="RV32F"/>
  <includes name="RV64I"/>
 </revision>
 <revision name="RV32D"/>
 <revision name="RV32DC">
  <includes name="RV32D"/>
 </revision>
 <revision name="RV64D">
  <includes name="RV32D"/>
  <includes name="RV64I"/>
 </revision>
 <revision name="RV32V"/>
 <revision name="RV32"/>
 <revision name="RV32FULL">
  <includes name="RV32I"/>
  <includes name="RV32M"/>
  <includes name="RV32A"/>
  <includes name="RV32F"/>
  <includes name="RV32C"/>
  <includes name="RV32FC"/>
  <includes name="RV32V"/>
  <includes name="RV32"/>
 </revision>
 <revision name="RV64C">
  <includes name="RV32C"/>
  <includes name="RV32FC"/>
  <includes name="RV32DC"/>
 </revision>
 <revision name="RV64"/>
 <revision name="RV64FULL">
  <includes name="RV64I"/>
  <includes name="RV64M"/>
  <includes name="RV64A"/>
  <includes name="RV64F"/>
  <includes name="RV32D"/>
  <includes name="RV64D"/>
  <includes name="RV64C"/>
  <includes name="RV32DC"/>
  <includes name="RV32V"/>
  <includes name="RV64"/>
  <excludes name="MEM_SV32"/>
 </revision>
</revisions>

Сборка:
specRevision=RV64FULL

Шаблон instruction_lw_sw_sv32.rb:

  def run
    if is_rev('MEM_SV32') then
      # Only for Sv32, (RV32)
      # csrwi satp, 0x80000002 # MODE = 1, PPN = 0x2
      trace "CSR satp = 0x%x", satp
      li t0, 0x800bed22
      trace "Register t0 = 0x%x", t0
      csrw satp, t0
      trace "CSR satp = 0x%x", satp

      li s0, 0x00010000 # Address
      prepare t0, 0xFFFFFFFFDEADBEEF # Value being loaded/stored

      trace "Register s0 = 0x%x", s0
      lw t1, s0, 0x0
      trace "Register t1 = 0x%x", t1
      sw t0, s0, 0x0
      trace "Register t0 = 0x%x", t0
      lw t1, s0, 0x0
      trace "Register t1 = 0x%x", t1
      nop
    end
  end

Симуляция:

1:
CSR satp = 0x0
0x00000000800000fc li t0, 0x800bed22
Register t0 = 0x800bed22
0x000000008000011c csrw satp, t0
CSR satp = 0x800bed22
0x0000000080000120 li s0, 0x10000
0x0000000080000128 li t0, 0xffffffffdeadbeef
Register s0 = 0x10000
0x0000000080000130 lw t1, 0(s0)
Mmu.PreTranslateAddress: satp.mode=0 (off)
Register t1 = 0x0
0x0000000080000134 sw t0, 0(s0)
Mmu.PreTranslateAddress: satp.mode=0 (off)
Register t0 = 0xffffffffdeadbeef
0x0000000080000138 lw t1, 0(s0)
Mmu.PreTranslateAddress: satp.mode=0 (off)
Register t1 = 0xffffffffdeadbeef
0x000000008000013c nop

Должно быть:

Работает корректно при:

 <revision name="RV64FULL">
  <includes name="RV64I"/>
  <includes name="RV64M"/>
  <includes name="RV64A"/>
  <includes name="RV64F"/>
  <includes name="RV32D"/>
  <includes name="RV64D"/>
  <includes name="RV64C"/>
  <includes name="RV32DC"/>
  <includes name="RV32V"/>
  <includes name="RV64"/>
  <excludes name="MEM_SV32"/>
 </revision>