MicroTESK is a reconfigurable (retargetable and extendable) model-based test program generator (TPG) for microprocessors and other programmable devices (such kind of tools are also called instruction stream generators or ISG). The generator is customized with the help of instruction-set architecture (ISA) specifications and configuration files, which describe parameters of the microprocessor subsystems (pipeline, memory and others). The suggested approach eases the model development and makes it possible to apply the model-based testing in the early design stages when the microprocessor architecture is frequently modified.
The current version of the tool supports ISA specification (in nML) and manual development of test program templates (in Ruby). It also implements lightweight methods for automated test program generation, including random-based and combinatorial techniques. Facilities for describing memory management units and microprocessor pipelines (microarchitectural networks) are under development, and so are the methods for advanced test program generation. The framework is applicable to a wide range of microprocessor architectures including RISC (ARM, MIPS, RISC-V, etc.), CISC (x86, etc.), and exotic ones (VLIW/EPIC, DSP, GPU, etc.).
|Office||25 Alexander Solzhenitsyn st., rooms 210 and 211, Moscow, 109004, Russia|
Licensing and Distribution¶
The MicroTESK package (consisting of MicroTESK core and sample ISA models) is distributed under the Apache License, Version 2.0, which implies the freedom to use the software for any purpose (to distribute it, to modify it and to distribute modified versions of the software) under the terms of the license, but requires preservation of the copyright notice and disclaimer.
The package can be downloaded from the Files page.
If you are looking for an industrial-level TPG/ISG for a particular architecture, contact us. We have a number of predefined ISA models as well as test engines for microprocessor verification. We also provide commercial services on developing MicroTESK-based specifications and generators.
Available ISA Models¶
|ARM||v8, AArch64||Closed||~1200 instructions|
|MIPS||Release 6||Open||~250 instructions|
|Power||PowerISA v.2.06||Closed||~120 instructions|
|RISC-V||Version 2.2||Open||~250 instructions|
|TestBase||Apache License, 2.0||Storing/retrieving test situations|
|Fortress||Apache License, 2.0||Representing expressions and solving constraints|
|Castle||Apache License, 2.0||Developing translators and code generators|
|Java SoftFloat||Apache License, 2.0||Performing IEEE 754 floating-point operations|
|ANTLR3||BSD License||Parsing nML/mmuSL specifications|
|Commons CLI||Apache License, 2.0||Parsing command line options|
|JRuby||Ruby License||Processing test templates|
|JUnit||Eclipse Public License, 1.0||Testing project classes|
MicroTESK 2.4.46 released
MicroTESK 2.4.46 has been released.
MicroTESK 2.4.45 released
MicroTESK 2.4.45 has been released.
MicroTESK 2.4.44 released
MicroTESK 2.4.44 has been released.
MicroTESK 2.4.43 released
MicroTESK 2.4.43 has been released.
MicroTESK 2.4.42 released
MicroTESK 2.4.42 has been released.
Manager: Alexander Kamkin
Project Creator: Alexander Kamkin