Task #5673
closedMemory scalability for large memory ranges (address space for 48 and 64 bit addresses)
100%
Description
Verify and review (if needed) the scalability of memory in the simulator for large memory ranges (address space for 48 and 64 bit addresses).
Question:
o ISPRAS to review and confirm the sparseness of the implementation of memory
• Does memory use of generation scale with number of locations touched or the range of (min, max)
Answer
In the current implementation of the simulator, memory is divided into 4KB regions which are allocated only when touched (written to).
Check whether the current way to avoid excessive memory consumption is sufficient. This includes more intensive testing. If not, the algorithm must be reviewed.
Basic ideas on sparse distributed memory:
Updated by Alexander Kamkin over 9 years ago
- Subject changed from [model] Memory scalability for large memory ranges (address space for 48 and 64 bit addresses) to Memory scalability for large memory ranges (address space for 48 and 64 bit addresses)
- Category set to ISA Simulator
- Target version set to 2.1
Updated by Alexander Kamkin over 9 years ago
- Category changed from ISA Simulator to 90
Updated by Alexander Kamkin over 9 years ago
- Target version changed from 2.1 to 2.2
Updated by Andrei Tatarnikov over 9 years ago
- Status changed from New to Resolved
Supported in microtesk-2.2.5-beta-150611.
Immediate values of arbitrary size will be supported in version 2.2.6 (r3871 - "Test templates: support for immediate values of arbitrary size (> 32 bit).")
Updated by Andrei Tatarnikov over 9 years ago
- Status changed from Resolved to Closed
- % Done changed from 0 to 100
- Published in build set to 150619