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Bug #9993
openif two modules are passed to the tool and one includes another, the tool hangs
Start date:
12/18/2019
Due date:
% Done:
0%
Estimated time:
Detected in build:
master
Platform:
Published in build:
Description
Suppose there are two files with Verilog modules: a.v and b.v (a.v contains "a" module, b.v contains "b" module). Module "a" includes module "b".
When the following args are used for the tool:
a.v b.v --include-path /path/to/b/file --module-name a
the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.
More adequate diagnostics should be shown here, and, of course, no freezes.
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