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Bug #8863
closedVerilogIeeeTestCase.runTest_17_02_04_4_1: java.lang.IllegalArgumentException
Start date:
05/07/2018
Due date:
% Done:
0%
Estimated time:
Detected in build:
master
Platform:
Published in build:
Description
The stack trace:
java.lang.IllegalArgumentException at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53) at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38) at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95) at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:111) at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:314) at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:331) at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:353) at ru.ispras.verilog.parser.processor.VerilogStaticChecker.onAssignStatementBegin(VerilogStaticChecker.java:106) at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265) at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700) at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100) at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85) at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80) at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56) at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163) at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45) at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813) at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799) at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_17_02_04_4_1(VerilogIeeeTestCase.java:1455)
The target Verilog module:
// IEEE Std 1364-2005
// 17. System tasks and functions
// 17.2 File input-output system tasks and functions
// 17.2.4 Reading data from a file
// 17.2.4.4 Reading binary data
// The example reads a binary data from the file specified by fd into the reg myreg or
// the memory mem. The start is an optional argument. If present, start shall be used as
// the address of the first element in the memory to be loaded. If not present, the lowest
// numbered location in the memory shall be used. The count is an optional argument. If
// present, count shall be the maximum number of locations in mem that shall be loaded. If
// not supplied, the memory shall be filled with what data are available. The start and
// count are ignored if $fread is loading a reg.
module test;
integer code, fd;
reg myreg, start;
integer count;
initial begin
code = $fread (myreg, fd);
code = $fread (mem, fd);
code = $fread (mem, fd, start);
code = $fread (mem, fd, start, count);
code = $fread (mem, fd, , count);
end
endmodule
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