Task #6976
closed
Added by Sergey Smolov about 8 years ago.
Updated over 7 years ago.
Published in build:
20161025
Description
Delete outdated info, add current models (HLDD) and analysis methods (model checking based).
- Status changed from New to Resolved
- % Done changed from 0 to 100
Add information about Verilog-related engines (other mentioned above are already added).
- Status changed from Resolved to Verified
- Status changed from Verified to Closed
- Detected in build changed from svn to master
- Published in build set to 20161025
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