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Bug #6892
closedsupport for non-zero starting bitvectors
Start date:
02/24/2016
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Platform:
Published in build:
20161025
Actions
Added by Sergey Smolov about 8 years ago. Updated over 7 years ago.
100%
Fixed for VHDL designs in cc972824.
For Verilog designs the following should be done: represent [max:min] vectors as [0:max-min] vectors and add related SHIFT meta-information that should be interpreted
upon NodeOperation objects construction.
Done for Verilog designs in f7fdaa6d.