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Task #5588

closed

extend HDL test suite

Added by Sergey Smolov over 9 years ago. Updated almost 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Test Suite
Target version:
1.0
Start date:
01/28/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:
1.1.1-beta-190722

Description

Extend a set of HDL (Verilog. VHDL) designs that are used as project test suite.

The collection of open-source benchmarks is available here: http://ddd.fit.cvut.cz/prj/Benchmarks/

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