Actions
Bug #10509
openERROR: [Internal] 0 must be > 0
Start date:
10/01/2020
Due date:
% Done:
0%
Estimated time:
Detected in build:
git
Platform:
Published in build:
Description
ERROR: [Internal] 0 must be > 0 java.lang.IllegalArgumentException: 0 must be > 0 at ru.ispras.fortress.util.InvariantChecks.checkGreaterThanZero(InvariantChecks.java:159) at ru.ispras.fortress.data.types.bitvector.BitVector.newEmpty(BitVector.java:381) at ru.ispras.verilog.parser.model.basis.VerilogLiteral.<init>(VerilogLiteral.java:188) at ru.ispras.verilog.parser.model.basis.VerilogLiteral.parseString(VerilogLiteral.java:55) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_string(VerilogTreeBuilder.java:7916) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:6628) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6502) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6356) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_task_statement(VerilogTreeBuilder.java:4716) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4393) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5465) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4473) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3514) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:1214) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:918) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_unit(VerilogTreeBuilder.java:765) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:713) at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:663) at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:455) at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:460) at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:486) at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:490) at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206) at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45) at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62) at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_usbf_top(VerilogIwlsTestSuite.java:4417)
Actions