Guarded actions extraction method » History » Revision 2
Revision 1 (Sergey Smolov, 03/09/2013 05:23 PM) → Revision 2/3 (Sergey Smolov, 03/09/2013 05:24 PM)
h1. Guarded actions extraction method h2. Concept The prototype of guarded actions extraction method is implemented in Retrascope project. This algorithm is based on IG representation of VHDL models, so guards and actions are extracted from corresponding IG constructions. It is IGSequentialAssignment classes for actions, and IGSequentialIf/IGSequentialWait constructions (more concrete, the conditions from these constructions) for guards. The method prototype is implemented in ru.ispras.retrascope.gaa.extraction.GAExtractor class. A small example of it''s possibilities you can see at ru.ispras.retrascope.gaa.tests.GAAExtractorTest test. This test: 1. Performs VHDL model into IG representation by using ZamiaCAD engine; 2. Calls method extractGuardedActions(ZamiaProject, IGModule) for actions and guards extraction; 3. Prints the result into console as list of pairs "guard-action" (also it is possible to save the result of the extraction into extracted_gaa.txt file) h2. Informal method description The algorithm walks through IG graph recursively. If it takes IGSequentialIf construction, it writes it''s condition into guard predicate. While analysis of this construction statements it is took into account are they executed when the guard is true (i.e. then-branch) or false (else-branch). Corresponding parts of the resulting guard predicate are stored with TRUE or FALSE labels. The directives themselves are also stored in accordance with guard predicates. Pairs "guard-action" are also extracted from assignment statements. h2. Implementation details The algorithm returns an object of java.util.ArrayList, which elements have type Guarded Action. This class keeps two main fields: Guard field and Action field. Both of them keeps code fragments in (if it is possible) constraint-based form. h2. Application area The algorithm can be applied both single module and multi-module VHDL design because of pecularities of ZamiaCAD (this engine performs multi=module VHDL design into single IG graph).