nML Language Reference¶

UNDER CONSTRUCTION

_{By Andrei Tatarnikov}

This reference manual describes syntax and semantics of the nML language. It covers language facilities supported by MicroTESK and does not attempt to be complete. It may differ from documentation provided by other vendors as there are differences in language implementations.

• Table of contents
• nML Language Reference
  • Introduction
  • Overview of nML

Introduction¶

nML_ is an architecture description language (ADL) used in MicroTESK to describe the architecture of a microprocessor under verification. It is a flexible and easy-to-use language based on attribute grammar. nML was designed to provide a retargetable way to specify microprocessor architecture for various microprocessor-related software tools including instruction-set simulators, assemblers, disassemblers, compiler back-ends etc. It works at the instruction-set level concentrating on behavioral properties and hiding implementation details. A nML specification represents a programmer''s model of the microprocessor which covers the following aspects:

• supported data types;
• registers and memory;
• addressing modes;
• syntax and semantics of instructions.

nML uses a hierarchical tree-like structure to describe an instruction set. Such a structure facilitates grouping related instructions and sharing their common parts. An instruction is described as a path in the tree from the root node to a leaf node. The set of all possible paths represents an instruction set. A node describes a primitive operation responsible for some task within an instruction. Each node has certain attributes that can be shared by its descendants. Actions performed by instructions are described as operations with registers and memory represented by bit vectors of arbitrary size.

A specification in nML starts with definitions of types and constants. For example, a type definition for a 32-bit word looks as follows:

let WORD_SIZE = 32
type word = card(WORD_SIZE)

Type definitions and constants can be used to describe registers and memory. In addition to registers and memory, it is also possible to define temporary variables that are internal abstractions provided by nML to store intermediate results of operations. They do not correspond to any data storage in real hardware and do not save their data across instruction calls. Also, there is often a need to specify some properties of the described model. For this purpose, special constants are used. For example, the code below defines general-purpose registers, memory and a temporary variable. Also, it includes a special constant to establish a correspondence between the general purpose register number 15 and the program counter (PC). Here is the code:

reg GPR[32, word]
mem M[2 ** 20, byte]
var carry[1, bit]
let PC = "GPR[15]"

As stated above, an instruction set is described as a tree of primitive operations. There two kinds of primitives: operations and addressing modes. Operations describe parts of instructions responsible for specific tasks and can be used as leaf and root nodes. Addressing modes are aimed to customize operations (for example, they encapsulate rules for accessing microprocessor resources). They can only be used as leaf nodes. For example, here are simplified examples of operation and addressing mode specifications:

mode REG(i: nibble) = R[i]
syntax = format("R%d", i)
image  = format("01%4b", i)

op Add()
syntax = "add" 
image  = "00" 
action = { DEST = SRC1 + SRC2; }

Operations and addressing modes have three standard attributes: syntax, image and action. The first two specify textual and binary syntax. The third describes semantics of the primitive. In addition, addressing modes have a return expression that enables them to be used as variables in various expressions. Attributes can be used by parent primitives referring to a given primitive to describe more complex abstractions.

Primitives are arranged into a tree using production rules. There are two kinds of production rules: AND rules and OR rules. AND rules specify parent-child relationships where a child primitive is described as a parameter of its parent. Here is an example of an AND rule:

op arith_inst(act: Add, op1: OPRND, op2: OPRND)

This is the header of the "arith_inst" operation that states that the "arith_inst" operation node has three child nodes: the "act" operation and the "op1" and "op2" addressing modes. The syntax of an operation header is similar to a function where parameter types specify the primitives the rule refers to. Parameter can be, in turn, parameterized with other primitives (they will be encapsulated behind attributes). For this reason child nodes represent independent instances that are accessed from their parent node via parameters. OR rules specify alternatives. This means that a group of primitives is united under some alias so that each of them can used when this alias is specified in an AND rule. An OR rule looks as follows:

op Add_Sub_Mov = Add | Sub | Mov

Figure 1 displays a tree path describing the "mov" instruction from an imaginary instruction set. This instruction copies data from one register to another. The root operation of the instruction is called “instruction”. According to nML conventions, the root operation is always called "instruction" and it specifies the point from which all paths describing specific instructions start. The "instruction" operation can be defined either as AND or OR rule. In the latter case, there are several starting points. Usually root operations holds some common properties and perform common actions (such as increment of the program counter). In the given example, the root operation is linked to the “Arithm” operation with the help of an AND rule. This operation describes a group of arithmetic operations. It is parameterized with the "Add_Mov_Sub" and "OPRND" primitives. Both of them are specified as OR rules. The first one describes arithmetic operations that can be performed by the "Arithm" primitive while the second one specifies supported addressing modes. Dashed lines that connect OR-rules with their child primitives specify possible alternative paths. Instructions are identified by the terminal operation node of the path (in this example, it is the "Mov" node). An important note is that, to avoid ambiguity, nodes can have only one child operation.

Figure 1. Operation tree for the Mov instruction

The syntax of nML resembles the syntax of the pseudocode used in microprocessor architecture manuals to describe instruction semantics. For example, here is the description of instruction ADD from the MIPS64 manual:

if NotWordValue(GPR[rs]) or NotWordValue(GPR[rt]) then
    UNPREDICTABLE
endif
temp ← GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0)
if temp32 ≠ temp31 then
    SignalException(IntegerOverflow)
else
    GPR[rd] ← sign_extend(temp31..0)
endif

Such a description can be translated to nML with minimal effort. Providing that all needed data types, resources and operations describing common functionality of instructions have already been specified, the specification of the ADD instruction (or, to be more precise, the terminal operation that distinguishes it from other similar instructions) will look as follows:

op ADD(rd: GPR, rs: GPR, rt: GPR)
action = {
    if (NotWordValue(rs) || NotWordValue(rt)) then
        UNPREDICTABLE();
    endif;
    tmp_word = rs<31>::rs<31..0> + rs<31>::rt<31..0>;
    if(tmp_word<32> != tmp_word<31>) then
        SignalException("IntegerOverflow");
    else
        rd = sign_extend(tmp_word<31..0>);
    endif;
}

As we can see, describing an instruction based on an instruction set manual is a relatively easy task that can be performed by a verification engineer who does not have significant programming skills.

Overview of nML¶