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Alexander Kamkin, 12/02/2014 07:41 AM


MMU Description

By Alexander Kamkin and Taya Sergeeva

A memory management unit (MMU) is known to be one of the most complex and error-prone components of a modern microprocessor. MicroTESK has a special subsystem, called MMU subsystem, intended for (1) specifying memory devices and (2) deriving testing knowledge from such specifications. The subsystem provides unified facilities for describing memory buffers (like L1 and L2 caches, translation look-aside buffers (TLBs), etc.) as well as a means for connecting several buffers into a memory hierarchy.

Grammar

startRule 
    : bufferOrAddress*
    ;

bufferOrAddress
    : address
    | buffer
    ;

The expression syntax is derived from nML/Sim-nML (see MicroTESK Language Reference).

Address Description

A buffer is accessed by an address, which is typically a bit vector of a fixed length (width). Different buffers are allowed to have a common address space (e.g., L1 and L2 are usually both addressed by physical addresses). However, in general case, each buffer has its own domain.

An address space is described using a keyword address. The description can specify two parameters: width (obligatory) and format (optional).

Grammar

address
    : ''address'' ID ''{''
        (addressParameter '';'')*
      ''}''
    ;

addressParameter
    : width
    | format
    ;

Address Width (width)

The width parameter specifies the address width. The parameter is obligatory; its value should be non-negative (zero-length addresses are permitted).

Grammar

width
    : ''width'' ''='' expr
    ;

Address Format (format)

The format parameter specifies the address format (a number of named fields). The parameter is optional. By default, the address is unstructured (no fields are specified).

A field has three attributes: a name, a width and, optionally, an initial value.

Grammar

format
    : ''format'' ''='' ''(''
        field ('','' field)*
      '')''
    ;

field
    : ID '':'' expr (''='' expr)?
    ;

Examples

// The singleton.
address Void {
  // The address width is zero (this is admissible for single-item buffers).
  width = 0;
}
// An unstructured 64-bit virtual addresses (VA).
address VA {
  // The address width.
  width = 64;
}
// A stuctured 40-bit physical addresses (PA).
address PA {
  // The address width.
  width = 40;
  // The address format: (<39..36>, TAG=<35..12>, INDEX=<11..5>, LOCAL=<4..0>).
  format = (
    TAG   : 24, // The tag (the <35..12> address bits).
    INDEX : 7,  // The set index (the <11..5> address bits).
    LOCAL : 5,  // The byte position (the <0..4> address bits).
  );
}

Buffer Description

A buffer is described using a keyword buffer. The description specifies a set of parameters, including ways, sets, format, index, match and policy. All of the parameters except index (if sets = 1) and policy are obligatory.

Grammar

buffer
    : ''buffer'' bufferTypeID ''{''
        (bufferParameter '';'')*
      ''}''
    ;

bufferParameter
    : ways
    | sets
    | format
    | index
    | match
    | policy
    ;

Buffer Associativity (ways)

The ways parameter specifies the buffer associativity (the number of lines in a set). The parameter is obligatory; its value should be positive.

Grammar

ways
    : ''ways'' ''='' expr
    ;

Buffer Length (sets)

The sets parameter specifies the buffer length (the number of sets a cache). The parameter is obligatory; its value should be positive.

Grammar

sets
    : ''sets'' ''='' expr
    ;

Buffer Line Format (format)

The format parameter specifies the buffer line format (a number of named fields). The parameter is optional. By default, the buffer line is unstructured (no fields are specified).

A field has three attributes: a name, a width and, optionally, an initial value.

Grammar

format
    : ''format'' ''='' ''('' field ('','' field)* '')''
    ;

field
    : fieldID '':'' expr (''='' expr)?
    ;

Buffer Index Function (index)

The index parameter specifies the address-to-index function, which maps an address into the set index. The function may be omitted if the number of sets is 1.

Grammar

index
    : ''index'' ''('' addressTypeID addressArgID '')'' ''='' expr
    ;

Buffer Match Predicate (match)

The match parameter specifies the address-line match predicate, which checks if an address matches a line. The parameter is obligatory.

Grammar

index
    : ''match'' ''('' addressTypeID addressArgID '')'' ''='' expr
    ;

Buffer Data Replacement Policy (policy)

The policy parameters specifies the data replacement (eviction) policy. The parameter is optional. The list of supported policies includes: RANDOM, FIFO, PLRU and LRU.

Grammar

policy
    : ''policy'' ''='' policyID
    ;

Examples

// A 4-way set associative cache (L1).
buffer L1 {
  // The cache associativity.
  ways = 4;
  // The number of sets.
  sets = 128;
  // The line format.
  format = (
    V    : 1 = 0, // The validity flag (by default, the line is invalid).
    TAG  : 24,    // The tag (the <35..12> address bits).
    DATA : 256    // The data (4 double words).
  );
  // The address-to-index function.
  index(PA addr) = addr<11..5>;
  // The address-line predicate.
  match(PA addr) = addr<35..12> == TAG;
  // The data replacement policy (LRU, Least Recently Used).
  policy = LRU;
}

Updated by Alexander Kamkin over 9 years ago · 89 revisions