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RISC-V Instruction Set » History » Revision 9

Revision 8 (Andrei Tatarnikov, 05/09/2018 05:06 PM) → Revision 9/50 (Andrei Tatarnikov, 05/09/2018 05:13 PM)

h1. RISC-V Instruction Set 

 {font-weight:bold; background:#ddd}. |/2. *Category* |\2. *RISC-V (Version 2.2)* |\2. *MicroTESK* | 
 {background:#dde}. | *Instructions* | *Amount* | *Instructions* | *Amount* | 
 {background:#fcc}. | Arithmetic Logic Unit | ADDI 
 SLTI 
 SLTIU 
 XLEN 
 ANDI 
 ORI 
 XORI 
 SRLI 
 SLLI 
 LUI 
 AUIPC 
 ADD 
 SUB 
 SLT 
 SLTU 
 AND 
 OR 
 XOR 
 SLL 
 SRL 
 SRA | 21+ |    | 0+ | 
 {background:#fcc}. | Branch| JAL 
 JALR 
 BEQ 
 BNE 
 BLT 
 BLTU 
 BGE 
 BGEU 
 BGT 
 BGTU 
 BLE 
 BLEU 
 BLT 
 BLTU 
 BGE 
 BGEU | 16 |    | 0+ | 
 {background:#ff9}. | Memory Access | LW 
 LH 
 LHU 
 LB 
 LBU 
 SW 
 SH 
 SB | 8 |    | 0 | 
 {background:#fcc}. | System | CSRRW 
 CSRRS 
 CSRRC 
 CSRRWI 
 CSRRSI 
 CSRRCI 
 RDCYCLE 
 RDTIME 
 RDINSTRET | 9 |    | 0 | 
 {background:#cfc}. | Other | NOP | 1 | NOP | 1 | 
 {background:#ddd}. | Total: || 65 |    | 1+ | 

 {background:#cfc}. |100%| 
 {background:#ff9}. |50+%| 
 {background:#fcc}. |0+%| 


 h1. Instructions supported by MicroTESK for RISC-V 

 {font-weight:bold; background:#ddd}. | Instruction Set | Instructions | Amount | 
 | RV32I     |    |    ?    | 
 | RV64I     |    |    ? | 
 | RV32M |    |    ?    | 
 | RV64M |    |    ?    | 
 | RV32A    |    |    ?    | 
 | RV64A    |    |    ?    | 
 | RV32F    |    |    26 ?    | 
 {background:#cfc}. | RV64F    |    FCVT.L.S 
                                                    FCVT.LU.S 
                                                    FCVT.S.L 
                                                    FCVT.S.LU |    4 ?    | 
 {background:#cfc}. | RV32D    | FLD 
                                                    FSD 
                                                    FMADD.D 
                                                    FMSUB.D 
                                                    FNMSUB.D 
                                                    FNMADD.D 
                                                    FADD.D 
                                                    FSUB.D 
                                                    FMUL.D 
                                                    FDIV.D 
                                                    FSQRT.D 
                                                    FSGNJ.D 
                                                    FSGNJN.D 
                                                    FSGNJX.D 
                                                    FMIN.D 
                                                    FMAX.D 
                                                    FCVT.S.D 
                                                    FCVT.D.S 
                                                    FEQ.D 
                                                    FLT.D 
                                                    FLE.D 
                                                    FCLASS.D 
                                                    FCVT.W.D 
                                                    FCVT.WU.D 
                                                    FCVT.D.W 
                                                    FCVT.D.WU |    26    | 
 {background:#cfc}. | RV64D    | FCVT.L.D 
                                                    FCVT.LU.D 
                                                    FMV.X.D 
                                                    FCVT.D.L 
                                                    FCVT.D.LU 
                                                    FMV.D.X          |     6    | 
 {background:#ddd}. | Total |    |     | 

 {background:#cfc}. |    Fully supported | 
 {background:#ff9}. |    Stub implementation | 
 {background:#fcc}. |    Unsupported |