RISC-V Instruction Set » History » Revision 38
Revision 37 (Andrei Tatarnikov, 07/26/2018 05:09 PM) → Revision 38/50 (Andrei Tatarnikov, 07/26/2018 05:25 PM)
h1. Instructions supported by MicroTESK for RISC-V The table below shows the state of support for particular instructions in MicroTESK for RISC-V. There are three stages of support marked with different colors: {background:#cfc}. | Fully supported | {background:#ff9}. | Partially supported | {background:#fcc}. | Currently unsupported | {font-weight:bold; background:#ddd}. | Instruction Set | Instructions | Specified | Validated | {background:#cfc}. | *RV32I (User)* | LUI AUIPC JAL JALR BEQ BNE BLT BGE BLTU BGEU LB LH LW LBU LHU SB SH SW ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SRAI SLL SRL SRA ADD SUB SLT SLTU XOR OR AND | Yes (37/37) | Yes (37/37) | {background:#cfc}. | *RV64I (User)* | LWU LD SD ADDIW SLLIW SRLIW SRAIW ADDW SUBW SLLW SRLW SRAW | Yes (12/12) | Yes (12/12) | {background:#ff9}. | *RV32I (System)* | ECALL EBREAK FENCE FENCE.I MRET SRET URET WFI CSRRW CSRRS CSRRC CSRRWI CSRRSI CSRRCI | Yes (14/14) | No (0/14) | {background:#cfc}. | *RV32M* | MUL MULH MULHSU MULHU DIV DIVU REM REMU | Yes (8/8) | Yes (8/8) | {background:#cfc}. | *RV64M* | MULW DIVW DIVUW REMW REMUW | Yes (5/5) | Yes (5/5) | {background:#cfc}. | *RV32A* | LR.W SC.W AMOSWAP.W AMOADD.W AMOXOR.W AMOAND.W AMOOR.W AMOMIN.W AMOMAX.W AMOMINU.W AMOMAXU.W | Yes (11/11) | Yes (11/11) | {background:#cfc}. | *RV64A* | LR.D SC.D AMOSWAP.D AMOADD.D AMOXOR.D AMOAND.D AMOOR.D AMOMIN.D AMOMAX.D AMOMINU.D AMOMAXU.D | Yes (11/11) | Yes (11/11) | {background:#ff9}. | *RV32F* | FLW FSW FMADD.S FMSUB.S FNMSUB.S FNMADD.S FADD.S FSUB.S FMUL.S FDIV.S FSQRT.S FSGNJ.S FSGNJN.S FSGNJX.S FMIN.S FMAX.S FCVT.W.S FCVT.WU.S FMV.X.W (FMV.X.S) FEQ.S FLT.S FLE.S FCLASS.S FCVT.S.W FCVT.S.WU FMV.W.X (FMV.S.X) | Yes (26/26) | Partially (8/26) Including (8): FLW FSW FEQ_S FLE_S FLT_S FEQ_S FLE_S FLT_S | {background:#ff9}. | *RV64F* | FCVT.L.S FCVT.LU.S FCVT.S.L FCVT.S.LU | Yes (4/4) | Partially (0/4) | {background:#ff9}. | *RV32D* | FLD FSD FMADD.D FMSUB.D FNMSUB.D FNMADD.D FADD.D FSUB.D FMUL.D FDIV.D FSQRT.D FSGNJ.D FSGNJN.D FSGNJX.D FMIN.D FMAX.D FCVT.S.D FCVT.D.S FEQ.D FLT.D FLE.D FCLASS.D FCVT.W.D FCVT.WU.D FCVT.D.W FCVT.D.WU | Yes (26/26) | Partially (2/26) Including (2): FLD FSD | {background:#ff9}. | *RV64D* | FCVT.L.D FCVT.LU.D FMV.X.D FCVT.D.L FCVT.D.LU FMV.D.X | Yes (6/6) | No (0/6) | {background:#ff9}. | *RVC* | C.ADDI4SPN C.FLD C.LQ C.LW C.FLW C.LD C.FSD C.SQ C.SW C.FSW C.SD C.NOP C.ADDI C.JAL C.ADDIW C.LI C.ADDI16SP C.LUI C.SRLI C.SRLI64 C.SRAI C.SRAI64 C.ANDI C.SUB C.XOR C.OR C.AND C.SUBW C.ADDW C.J C.BEQZ C.BNEZ C.SLLI C.SLLI64 C.FLDSP C.LQSP C.LWSP C.FLWSP C.LDSP C.JR C.MV C.EBREAK C.JALR C.ADD C.FSDSP C.SQSP C.SWSP C.FSWSP C.SDSP | Yes (49/49) | Partially (36/49) Excluding (13): C.LQ C.FLW C.SQ C.FSW C.NOP C.SRLI64 C.SRAI64 C.SLLI64 C.LQSP C.FLWSP C.EBREAK C.SQSP C.FSWSP | {background:#fcc}. | *RV64Q* | | No | No | {background:#fcc}. | *RV32V* | VADD VSUB VSL VSR VAND VOR VXOR VSEQ VSNE VSLT VSGE VCLIP VCVT VMPOP VMFIRST VEXTRACT VINSERT VMERGE VSELECT VSLIDE VDIV VREM VMUL VMULH VMIN VMAX VSGNJ VSGNJN VSGNJX VSQRT VCLASS VPOPC VADDI VSLI VSRI VANDI VORI VXORI VCLIPI VMADD VMSUB VNMADD VNMSUB | No | No | {background:#ddd}. | Total | | | | {background:#cfc}. | Fully supported | {background:#ff9}. | Partially supported | {background:#fcc}. | Currently unsupported |