RISC-V Instruction Set » History » Revision 3
Revision 2 (Alexander Protsenko, 11/04/2016 12:51 PM) → Revision 3/50 (Alexander Protsenko, 11/04/2016 02:07 PM)
h1. RISC-V Instruction Set
{font-weight:bold; background:#ddd}. |/2. *Category* |\2. *RISC-V (Version 2.1)* |\2. *MicroTESK* |
{background:#dde}. | *Instructions* | *Amount* | *Instructions* | *Amount* |
{background:#fcc}. | Arithmetic Logic Unit | ADDI
SLTI
SLTIU
XLEN
ANDI
ORI
XORI
SRLI
SLLI
LUI
AUIPC
ADD
SUB
SLT
SLTU
AND
OR
XOR
SLL
SRL
SRA | 21+ | | 0+ |
{background:#fcc}. {background:#ff9}. | Branch| JAL
JALR
BEQ
BNE
BLT
BLTU
BGE
BGEU
BGT
BGTU
BLE
BLEU
BLT
BLTU
BGE
BGEU | 0+ | | 0+ |
{background:#ff9}. | Memory Access | | 0+ | | 0+ |
{background:#cfc}. | Other | NOP | 1 | NOP | 1 |
{background:#ddd}. | Total: || 0+ | | 0+ |
{background:#cfc}. |100%|
{background:#ff9}. |50+%|
{background:#fcc}. |0+%|