RISC-V Instruction Set » History » Revision 2
Revision 1 (Alexander Protsenko, 11/03/2016 11:49 PM) → Revision 2/50 (Alexander Protsenko, 11/04/2016 12:51 PM)
h1. RISC-V Instruction Set
{font-weight:bold; background:#ddd}. |/2. | *Category* |\2. *RISC-V (Version 2.1)* |\2. *MicroTESK* |
{background:#dde}. | *Instructions* | *Amount* | *Instructions*
{background:#cfc}. | *Amount* |
{background:#fcc}. | Arithmetic Logic Unit | ADDI | 0+ |
SLTI
SLTIU
XLEN
ANDI
ORI
XORI
SRLI
SLLI
LUI
AUIPC
ADD
SUB
SLT
SLTU
AND
OR
XOR
SLL
SRL
SRA {background:#fcc}. | 21+ Shifter | | 0+ |
{background:#ff9}. {background:#fcc}. | Branch| Multiply| | 0+ |
{background:#ff9}. | Branch| | 0+ |
{background:#ff9}. | Memory Access | | 0+ | | 0+ |
{background:#cfc}. | Other | NOP | 1 | NOP | 1 |
{background:#ddd}. | Total: || 0+ | | 0+ |
{background:#cfc}. |100%|
{background:#ff9}. |50+%|
{background:#fcc}. |0+%|