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Task #9670

open

add 'ar.v' module to the test suite when SVA support will be implemented

Added by Sergey Smolov almost 5 years ago. Updated about 4 years ago.

Status:
New
Priority:
High
Assignee:
Sergey Smolov
Category:
Verilog Translator
Start date:
05/22/2019
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Published in build:

Description

See Ver2SmvBenchmarks test class.

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