MMU description » History » Revision 128
Revision 127 (Andrei Tatarnikov, 01/29/2015 04:24 PM) → Revision 128/132 (Alexander Kamkin, 02/06/2015 07:20 AM)
h1. MMU Description _~By Alexander Kamkin, Kamkin and Taya Sergeeva, and Andrei Tatarnikov~_ Sergeeva~_ {{toc}} A _memory management unit_ (_MMU_) is known to be one of the most complex and error-prone components of a modern microprocessor. MicroTESK has a special subsystem, called _MMU subsystem_, intended for (1) specifying memory devices and (2) deriving testing knowledge from such specifications. The subsystem provides unified facilities for describing memory buffers (like _L1_ and _L2 caches_, _translation look-aside buffers_ (_TLBs_), etc.) as well as a means for connecting several buffers into a memory hierarchy. h2. Grammar <pre> startRule : declaration* EOF! ; declaration : address | segment | buffer | mmu ; </pre> The expression syntax is derived from nML/Sim-nML (see [[Sim-nML Language Reference]]). h2. Address Description (address) A buffer is accessed by an _address_, which is typically a _bit vector_ of a fixed length (width). Different buffers are allowed to have a common address space (e.g., L1 and L2 are usually both addressed by physical addresses). However, in general case, each buffer has its own domain. An address space is described using a keyword @address@. The description includes the address type _identifier_ and the address _width_. The latter is specified in brackets. Its value should be non-negative (zero-length addresses are permitted). h3. Grammar <pre> address : ''address'' addressTypeID ''('' expr '')'' ; </pre> h3. Examples <pre>// A 64-bit virtual address (VA). address VA(64)</pre> <pre>// A 36-bit physical address (PA). address PA(36)</pre> h2. Address Space Segment Description (segment) An address space segment is specified using the @segment@ keyword. A segment is associated with a specific address type. It is possible to specify any number (≥ 0) of segments (with different names) for one address type. Each segment is characterized by its _identifier_ and _address range_. Different segments should have different names, but address ranges are allowed to overlap, and moreover, to be the same. h3. Grammar <pre> segment : ''segment'' segmentID ''('' argumentID '':'' addressTypeID '')'' ''range'' ''='' ''('' expr '','' expr '')'' ; </pre> h3. Examples <pre> segment USEG (va: VA) range = (0x0000000000000000, 0x000000007fffffff) </pre> h2. Buffer Description (buffer) A buffer is described using a keyword @buffer@. The description specifies a set of parameters, including @ways@, @sets@, @entry@, @index@, @match@ and @policy@. All of the parameters except @index@ (if @sets = 1@) and @policy@ are obligatory. h3. Grammar <pre> buffer : ''buffer'' bufferTypeID ''('' addressArgID '':'' addressTypeID '')'' (bufferParameter)* ; bufferParameter : ways | sets | entry | index | match | policy ; </pre> h3. Buffer Associativity (ways) The @ways@ parameter specifies the buffer _associativity_ (the number of lines in a set). The parameter is obligatory; its value should be positive. h4. Grammar <pre> ways : ''ways'' ''='' expr ; </pre> h3. Buffer Length (sets) The @sets@ parameter specifies the buffer _length_ (the number of sets a cache). The parameter is obligatory; its value should be positive. h4. Grammar <pre> sets : ''sets'' ''='' expr ; </pre> h3. Buffer Line Format (entry) The @entry@ parameter specifies the buffer _line format_ (a number of named fields). A field has three attributes: a name, a width and, optionally, an initial value. h4. Grammar <pre> format : ''entry'' ''='' ''('' field ('','' field)* '')'' ; field : fieldID '':'' expr (''='' expr)? ; </pre> h3. Buffer Index Function (index) The @index@ parameter specifies the _address-to-index function_, which maps an address into the set index. The function may be omitted if the number of sets is @1@. h4. Grammar <pre> index : ''index'' ''='' expr ; </pre> h3. Buffer Match Predicate (match) The @match@ parameter specifies the _address-line match predicate_, which checks if an address matches a line. The parameter is obligatory. h4. Grammar <pre> index : ''match'' ''='' expr ; </pre> h3. Buffer Data Replacement Policy (policy) The @policy@ parameters specifies the _data replacement_ (_eviction_) _policy_. The parameter is optional. The list of supported policies includes: @RANDOM@, @FIFO@, @PLRU@ and @LRU@. h4. Grammar <pre> policy : ''policy'' ''='' policyID ; </pre> h3. Examples <pre> // A 4-way set associative cache (L1) addressed by physical addresses (PA). buffer L1(addr: PA) // The cache associativity. ways = 4 // The number of sets. sets = 128 // The line format. entry = ( V : 1 = 0, // The validity flag (by default, the line is invalid). TAG : 24, // The tag (the <35..12> address bits). DATA : 256 // The data (4 double words). ) // The address-to-index function (example: using address fields). index = addr.INDEX // The address-line predicate (example: using address bits). match = addr<35..12> == TAG // The data replacement policy (example: using predefined policy LRU - Least Recently Used). policy = LRU </pre> h2. MMU Description (mmu) Memory management unit logic is described using the @mmu@ keyword. The description includes two obligatory parameters @read@ and @write@ that describe the semantics of memory read and memory write actions respectively. h3. Grammar <pre> mmu : ''mmu'' memoryTypeID ''('' addressArgID '':'' addressTypeID '')'' = dataArgID (mmuVariable)* (mmuParameter)* ; mmuVariable : ''var'' variableID '':'' variableTypeID (''.'' ''entry'')? '';'' ; mmuParameter : read | write ; </pre> h3. Memory Read Action (read) The @read@ parameter specifies the _read action_, which is a sequence of statements describing how the read operation is to be performed (by means of data transfers between buffers). The parameter is obligatory. h4. Grammar <pre> read : ''read'' ''='' ''{'' sequence ''}'' ; </pre> h3. Memory Write Action (write) The @write@ parameter specifies the _read action_, which is a sequence of statements describing how the write operation is to be performed (by means of data transfers between buffers). The parameter is obligatory. h4. Grammar <pre> write : ''write'' ''='' ''{'' sequence ''}'' ; </pre> h3. Examples <pre> // A memory unit addressed by virtual addresses (VA). mmu Memory(addr: VA) = data // The read action. read = { // Some statements. ... } // The write action. write = { // Some statements. ... } </pre>