Project

General

Profile

Actions
Copy link

Task #11018

open

Verilog duplicate removing

Added by Sergey Smolov almost 3 years ago.

Status:
New
Priority:
Normal
Assignee:
Sergey Smolov
Category:
-
Start date:
11/27/2021
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Published in build:

Description

Remove Verilog modules that appear in two or more test collections (Texas-97, VCEGAR or Verilog2SMV).

No data to display

Actions
Copy link

Also available in: Atom PDF