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Bug #9514
closedNet declaration assignment is a continuous assignment
Start date:
03/01/2019
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.2-beta-190909
Description
According to the Verilog 2005 standard, net declaration assignment is a form of a continuous assignment. Veritrans handles it as an initial value assignment, not as a process.
Chapter 6.1.1 of the standard:
... the net declaration assignment, allows a continuous assignment to be placed on a net in the same statement that declares the net.
The following is an example of the net declaration form of a continuous assignment:
wire (strong1, pull0) mynet = enable ;
...
See test_06_01_01_1
.
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