Alexey Danilov
- Login: aadanilov
- Registered on: 09/06/2019
- Last connection: 05/28/2021
Issues
| open | closed | Total | |
|---|---|---|---|
| Assigned issues | 0 | 10 | 10 |
| Reported issues | 0 | 4 | 4 |
Projects
| Project | Roles | Registered on |
|---|---|---|
| Verilog Translator | Developer | 10/22/2019 |
Activity
04/08/2020
- 06:28 PM Verilog Translator Bug #10237 (Resolved): ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v'
- 05:44 PM Verilog Translator Bug #10216 (Resolved): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException
04/02/2020
- 04:25 PM Verilog Translator Bug #10173 (Resolved): javadoc: DefineStructure.java:37: warning: no @return
- 04:24 PM Verilog Translator Bug #10141 (Resolved): check port redeclarations
- 04:24 PM Verilog Translator Feature #9990 (Resolved): check for variable/net redeclarations
04/01/2020
- 10:43 AM Verilog Translator Bug #10197 (Closed): Test const.v has an error.
- ERROR: Node 'g' has been declared two or more times
- 10:42 AM Verilog Translator Bug #10196 (Closed): Test mpeg1.v has an error.
- ERROR: Port 'clk' has been declared two or more times in module 'counter'.
- 10:41 AM Verilog Translator Bug #10195 (Closed): Test test_12_04_02_4.v has an error.
- ERROR: Port 'udqm' has been declared two or more times in module 'sms_08b216t0'.
- 10:40 AM Verilog Translator Bug #10194 (Closed): Test test_07_14_02_2_1.v has an error
- ERROR: Node 'cap1' has been declared two or more times
03/03/2020
- 02:40 PM Verilog Translator Feature #9990 (Open): check for variable/net redeclarations
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