Open-Source Projects

04/02/2020

04:25 PM Verilog Translator Bug #10173 (Resolved): javadoc: DefineStructure.java:37: warning: no @return

Alexey Danilov

04:24 PM Verilog Translator Bug #10141 (Resolved): check port redeclarations

Alexey Danilov

04:24 PM Verilog Translator Feature #9990 (Resolved): check for variable/net redeclarations

Alexey Danilov

04/01/2020

10:43 AM Verilog Translator Bug #10197 (Resolved): Test const.v has an error.

ERROR: Node 'g' has been declared two or more times
Alexey Danilov

10:42 AM Verilog Translator Bug #10196 (Resolved): Test mpeg1.v has an error.

ERROR: Port 'clk' has been declared two or more times in module 'counter'.
Alexey Danilov

10:41 AM Verilog Translator Bug #10195 (Resolved): Test test_12_04_02_4.v has an error.

ERROR: Port 'udqm' has been declared two or more times in module 'sms_08b216t0'.
Alexey Danilov

10:40 AM Verilog Translator Bug #10194 (Resolved): Test test_07_14_02_2_1.v has an error

ERROR: Node 'cap1' has been declared two or more times Alexey Danilov

03/03/2020

02:40 PM Verilog Translator Feature #9990 (Open): check for variable/net redeclarations

Alexey Danilov

02:35 PM Verilog Translator Feature #9990 (Resolved): check for variable/net redeclarations

Alexey Danilov

12/17/2019

07:01 PM Verilog Translator Bug #9962 (Resolved): ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException

Alexey Danilov