Alexey Danilov - Open-Source Projects

Alexey Danilov

Registered on: 09/06/2019
Last connection: 01/13/2020

Issues

Assigned issues: 4
Reported issues: 0

Projects

Verilog Translator (Developer, 10/22/2019)

Activity

12/17/2019

07:01 PM Verilog Translator Bug #9962 (Resolved): ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException: Alexey Danilov

12/03/2019

05:52 PM Verilog Translator Bug #9936 (Resolved): tabs in "`define" directive cause java.lang.NumberFormatException: Alexey Danilov
02:37 PM Verilog Translator Task #9811 (Resolved): macro with parameters: Alexey Danilov
02:36 PM Verilog Translator Bug #9915 (Resolved): "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file: Alexey Danilov

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