Verilog Translator

h1. Some Details

h2. Variable Declarations

Each declaration has a set of namesakes (declarations with the same name). Take a look to an example below.

<pre><code class="c">

// A variable can be an _output_ and a _register_ (or a _wire_) at the same time.

output var;

reg var;

</code></pre>

In this case, two declarations will be created:

# ⟨ _ID_ ~1~, _name_ = "var", _type_ = "output", _namesakes_ = { _ID_ ~2~ } ⟩

# ⟨ _ID_ ~2~, _name_ = "var", _type_ = "output", _namesakes_ = { _ID_ ~1~ } ⟩

The job is carried out by the _redefiniton handler_ attached to the _symbol table_. Being requested with some name, the table checks whether it contains an entity with the given name. if it does, the redefinition handler is invoked, which does nothing unless the entities are declarations; for declarations, it updates the sets of namesakes.