Verilog Translator

h1. Some Details

h2. Variable Declarations

Each declaration has a set of namesakes (declarations with the same name). Take a look to an example below.

<pre><code class="c">

// A variable can be an output and a register (or a wire) at the same time.

output var;

reg var;

</code></pre>

In this case, two declarations will be created:

# ⟨ _ID_ ~1~, _name_ = "var", _type_ = "output", _namesakes_ = { _ID_ ~2~ } ⟩

# ⟨ _ID_ ~2~, _name_ = "var", _type_ = "output", _namesakes_ = { _ID_ ~1~ } ⟩