Verilog Translator

h1. Icarus Verilog Bugs

The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests").

# test_03_08_01_1.v

<pre>

test_03_08_01_1.v:25: syntax error

test_03_08_01_1.v:27: error: malformed statement

test_03_08_01_1.v:28: syntax error

test_03_08_01_1.v:33: error: malformed statement

test_03_08_01_1.v:34: syntax error

test_03_08_01_1.v:39: error: malformed statement

test_03_08_01_1.v:40: syntax error

</pre>

*Cause*: attributes for "case" statement branches like "(* full_case, parallel_case *)" are unsupported.

# test_03_08_01_2.v

<pre>

test_03_08_01_2.v:25: syntax error

test_03_08_01_2.v:27: error: malformed statement

test_03_08_01_2.v:28: syntax error

test_03_08_01_2.v:32: error: malformed statement

test_03_08_01_2.v:33: syntax error

</pre>

*Cause*: attributes for "case" statement branches like "(* full_case *)" are unsupported.

# test_03_08_01_6.v

<pre>

test_03_08_01_6.v:25: syntax error

test_03_08_01_6.v:25: error: malformed statement

</pre>

*Cause*: attributes for assignments like "a = b + (* mode = "cla" *) c;" are unsupported.

# test_03_08_01_7.v

<pre>

test_03_08_01_7.v:25: syntax error

test_03_08_01_7.v:25: error: malformed statement

</pre>

*Cause*: attributes for assignments like "a = add (* mode = "cla" *) (b, c);" are unsupported.

# test_03_08_01_8.v

<pre>

test_03_08_01_8.v:25: syntax error

test_03_08_01_8.v:25: error: malformed statement

</pre>

*Cause*: attributes for assignments like "a = b ? (* no_glitch *) c : d;" are unsupported.

# test_04_03_01_1.v

<pre>

test_04_03_01_1.v:24: sorry: trireg nets not supported.

</pre>

*Cause*: cannot parse "trireg (small) storeit;"

# test_04_03_02_1.v

<pre>

test_04_03_02_1.v:22: syntax error

test_04_03_02_1.v:22: error: invalid module item.

test_04_03_02_1.v:23: syntax error

test_04_03_02_1.v:23: error: invalid module item.

</pre>

*Cause*: cannot parse "tri1 scalared [63:0] bus64;"

# test_04_04_01_1.v

<pre>

test_04_04_01_1.v:22: sorry: trireg nets not supported.

test_04_04_01_1.v:23: sorry: trireg nets not supported.

test_04_04_01_1.v:25: syntax error

test_04_04_01_1.v:25: error: invalid module item.

</pre>

*Cause*: cannot parse "trireg a;"

# test_04_09_03_1_1.v

<pre>

test_04_09_03_1_1.v:26: sorry: only 1 dimensional arrays are currently supported.

test_04_09_03_1_1.v:28: sorry: only 1 dimensional arrays are currently supported.

</pre>

*Cause*: cannot parse "reg arrayb[7:0][0:255];"

# test_04_09_03_1_2.v

<pre>

test_04_09_03_1_2.v:26: sorry: only 1 dimensional arrays are currently supported.

test_04_09_03_1_2.v:28: sorry: only 1 dimensional arrays are currently supported.

</pre>

*Cause*: cannot parse "reg arrayb[7:0][0:255];"

# test_04_10_03_2.v

<pre>

test_04_10_03_2.v:23: syntax error

test_04_10_03_2.v:23: error: invalid module item.

test_04_10_03_2.v:24: syntax error

test_04_10_03_2.v:24: error: invalid module item.

</pre>

*Cause*: the "specparam" is unsupported.

# test_05_01_14_1.v

<pre>

test_05_01_14_1.v:30: error: Array b['sd3:'sd0] cannot be indexed by a range.

</pre>

*Cause*: cannot parse "result = {a, b[3:0], w, 3'b101};"

# test_05_02_01_4.v

<pre>

test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'

test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'

</pre>

*Cause*: cannot parse "addr = x;"

# test_05_02_02_2.v

<pre>

test_05_02_02_2.v:25: sorry: only 1 dimensional arrays are currently supported.

test_05_02_02_2.v:26: sorry: only 1 dimensional arrays are currently supported.

</pre>

*Cause*: cnnot parse "wire threed_array[0:255][0:255][0:7];"

# test_05_03_00_1.v

<pre>

test_05_03_00_1.v:25: warning: choosing typ expression.

</pre>

*Cause*: "parameter val = (32'd 50: 32'd 75: 32'd 100);"

# test_06_01_03_1.v

<pre>

test_06_01_03_1.v:24: sorry: net delays not supported.

</pre>

*Cause*: "wire #10 wireA;"

# test_07_14_01_1.v

<pre>

test_07_14_01_1.v:25: warning: choosing typ expression.

test_07_14_01_1.v:25: warning: choosing typ expression.

test_07_14_01_1.v:25: warning: choosing typ expression.

test_07_14_01_1.v:26: warning: choosing typ expression.

test_07_14_01_1.v:26: warning: choosing typ expression.

test_07_14_01_1.v:26: warning: choosing typ expression.

</pre>

*Cause*: "bufif0 #(5:7:9, 8:10:12, 15:18:21) b1 (io1, io2, dir);"

# test_07_14_01_2.v

<pre>

test_07_14_01_2.v:26: warning: choosing typ expression.

test_07_14_01_2.v:27: warning: choosing typ expression.

</pre>

*Cause*: " #(95:100:105) clk = 1;"

# test_07_14_02_2_1.v

<pre>

test_07_14_02_2_1.v:25: sorry: trireg nets not supported.

</pre>

*Cause*: "trireg ( large ) #(0,0,50) cap1;"

# test_07_14_02_2_2.v

<pre>

test_07_14_02_2_2.v:26: sorry: trireg nets not supported.

</pre>

*Cause*: "trireg ( large ) #(0,0,50) cap1;"

# test_08_06_00_1.v

<pre>

test_08_06_00_1.v:46: syntax error

test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.

test_08_06_00_1.v:46: error: Invalid module instantiation

*Cause*: "d_edge_ff #p3 d_inst (q, clock, data);"

</pre>

# test_08_07_00_1.v

<pre>

test_08_07_00_1.v:30: syntax error

</pre>

*Cause*: "    ?     ?? 01 : ? : 1 ;"

# test_09_06_00_1.v

<pre>

test_09_06_00_1.v:27: syntax error

test_09_06_00_1.v:28: error: invalid module item.

test_09_06_00_1.v:29: syntax error

test_09_06_00_1.v:29: error: Invalid module instantiation

test_09_06_00_1.v:30: error: Invalid module instantiation

test_09_06_00_1.v:31: error: Invalid module instantiation

test_09_06_00_1.v:34: error: invalid module item.

test_09_06_00_1.v:35: syntax error

test_09_06_00_1.v:35: error: Invalid module instantiation

test_09_06_00_1.v:36: error: Invalid module instantiation

</pre>

*Cause*: "begin : mult"

# test_09_06_00_2.v

<pre>

test_09_06_00_2.v:23: syntax error

test_09_06_00_2.v:24: error: invalid module item.

test_09_06_00_2.v:25: syntax error

test_09_06_00_2.v:25: error: Invalid module instantiation

test_09_06_00_2.v:26: error: Invalid module instantiation

test_09_06_00_2.v:29: error: invalid module item.

test_09_06_00_2.v:30: syntax error

test_09_06_00_2.v:30: error: Invalid module instantiation

</pre>

*Cause*: "begin : count1s"

# test_09_06_00_3.v

<pre>

test_09_06_00_3.v:27: syntax error

test_09_06_00_3.v:27: Syntax in assignment statement l-value.

test_09_06_00_3.v:28: syntax error

test_09_06_00_3.v:28: Syntax in assignment statement l-value.

test_09_06_00_3.v:35: syntax error

test_09_06_00_3.v:35: error: Incomprehensible for loop.

</pre>

# test_09_07_01_2.v

<pre>

test_09_07_01_2.v:30: syntax error

test_09_07_01_2.v:30: Syntax in assignment statement l-value.

</pre>

# test_09_07_05_1.v

<pre>

test_09_07_05_1.v:31: syntax error

</pre>

# test_09_07_05_2.v

<pre>

test_09_07_05_2.v:30: error: port y already has a port declaration.

test_09_07_05_2.v:29: error: Port ``y'' has already been declared a port.

</pre>

# test_09_07_05_3.v

<pre>

test_09_07_05_3.v:32: internal error: NetProc::nex_input not implemented

test_09_07_05_3.v:31: error: Unable to elaborate:

      @(test._s0)  // test_09_07_05_3.v:32

        {kid} = b[0:0];

</pre>

# test_09_07_05_4.v

<pre>

test_09_07_05_4.v:33: internal error: NetProc::nex_input not implemented

</pre>

# test_09_07_05_5.v

<pre>

test_09_07_05_5.v:32: error: y is not a valid l-value in test.

test_09_07_05_5.v:29:      : y is declared here as wire.

test_09_07_05_5.v:33: error: y[a] is not a valid l-value in test.

test_09_07_05_5.v:29:      : y[a] is declared here as wire.

test_09_07_05_5.v:31: warning: @* found no sensitivities so it will never trigger.

</pre>

# test_09_07_05_6.v

<pre>

test_09_07_05_6.v:35: error: Unable to bind wire/reg/memory `IDLE' in `test'

test_09_07_05_6.v:35: error: Unable to bind wire/reg/memory `READ' in `test'

test_09_07_05_6.v:36: error: Unable to bind wire/reg/memory `IDLE' in `test'

test_09_07_05_6.v:37: error: Unable to bind wire/reg/memory `READ' in `test'

test_09_07_05_6.v:37: error: Unable to bind wire/reg/memory `DLY' in `test'

test_09_07_05_6.v:38: error: Unable to bind wire/reg/memory `DLY' in `test'

test_09_07_05_6.v:38: error: Unable to bind wire/reg/memory `DONE' in `test'

</pre>

# test_09_07_06_1.v

<pre>

test_09_07_06_1.v:32: syntax error

test_09_07_06_1.v:33: error: invalid module item.

test_09_07_06_1.v:34: syntax error

test_09_07_06_1.v:34: error: invalid module item.

test_09_07_06_1.v:35: syntax error

</pre>

# test_09_07_07_1.v

<pre>

test_09_07_07_1.v:32: syntax error

</pre>

# test_09_07_07_3.v

<pre>

test_09_07_07_3.v:28: error: Unable to bind wire/reg/memory `clk' in `test'

test_09_07_07_3.v:33: error: Unable to bind wire/reg/memory `clk' in `test'

</pre>

# test_09_07_07_4.v

<pre>

test_09_07_07_4.v:29: error: Unable to bind wire/reg/memory `clk' in `test'

test_09_07_07_4.v:34: error: Unable to bind wire/reg/memory `clk' in `test'

test_09_07_07_4.v:35: error: Unable to bind wire/reg/memory `clk' in `test'

test_09_07_07_4.v:36: error: Unable to bind wire/reg/memory `clk' in `test'

</pre>

# test_09_07_07_9.v

<pre>

test_09_07_07_9.v:31: error: Unable to bind wire/reg/memory `data' in `test'

</pre>

# test_09_08_01_3.v

<pre>

test_09_08_01_3.v:33: error: event <end_wave> not found.

</pre>

# test_09_08_02_1.v

<pre>

test_09_08_02_1.v:35: error: event <end_wave> not found.

</pre>

# test_09_08_04_1.v

<pre>

test_09_08_04_1.v:29: error: event <end_wave> not found.

</pre>

# test_09_08_04_2.v

<pre>

:0: error: Unable to bind wire/reg/memory `Aevent' in `test'

:0: error: Unable to bind wire/reg/memory `Bevent' in `test'

</pre>

# test_09_08_04_3.v

<pre>

:0: error: Unable to bind wire/reg/memory `enable_a' in `test'

:0: error: Unable to bind wire/reg/memory `enable_b' in `test'

</pre>

# test_09_09_01_1.v

<pre>

test_09_09_01_1.v:27: error: signal and parameter in 'test' have the same name 'size'.

</pre>

# test_09_09_02_1.v

<pre>

test_09_09_02_1.v:26: error: always statement does not have any delay.

test_09_09_02_1.v:26:      : A runtime infinite loop will occur.

</pre>

# test_10_01_00_1.v

<pre>

test_10_01_00_1.v:29: syntax error

test_10_01_00_1.v:32: error: malformed statement

test_10_01_00_1.v:33: syntax error

</pre>

# test_10_01_00_2.v

<pre>

test_10_01_00_2.v:27: syntax error

test_10_01_00_2.v:30: Syntax in assignment statement l-value.

test_10_01_00_2.v:31: syntax error

</pre>

# test_10_02_02_1_1.v

<pre>

test_10_02_02_1_1.v:31: error: Could not find variable ``foo1'' in ``test.my_task''

test_10_02_02_1_1.v:32: error: Could not find variable ``foo1'' in ``test.my_task''

test_10_02_02_1_1.v:33: error: Could not find variable ``foo1'' in ``test.my_task''

test_10_02_02_1_1.v:34: error: Could not find variable ``foo1'' in ``test.my_task''

test_10_02_02_1_1.v:35: error: Unable to bind wire/reg/memory `foo1' in `test.my_task'

test_10_02_02_1_1.v:36: error: Unable to bind wire/reg/memory `foo2' in `test.my_task'

test_10_02_02_1_1.v:37: error: Unable to bind wire/reg/memory `foo3' in `test.my_task'

</pre>

# test_10_02_02_1_2.v

<pre>

test_10_02_02_1_2.v:27: error: Could not find variable ``foo1'' in ``test.my_task''

test_10_02_02_1_2.v:28: error: Could not find variable ``foo2'' in ``test.my_task''

test_10_02_02_1_2.v:29: error: Could not find variable ``foo3'' in ``test.my_task''

test_10_02_02_1_2.v:30: error: Unable to bind wire/reg/memory `foo1' in `test.my_task'

test_10_02_02_1_2.v:31: error: Unable to bind wire/reg/memory `foo2' in `test.my_task'

test_10_02_02_1_2.v:32: error: Unable to bind wire/reg/memory `foo3' in `test.my_task'

</pre>

# test_10_03_00_1.v

<pre>

test_10_03_00_1.v:25: syntax error

test_10_03_00_1.v:26: error: invalid module item.

test_10_03_00_1.v:27: syntax error

test_10_03_00_1.v:27: error: invalid module item.

test_10_03_00_1.v:28: syntax error

test_10_03_00_1.v:28: error: Invalid module instantiation

</pre>

# test_10_03_00_2.v

<pre>

test_10_03_00_2.v:27: syntax error

test_10_03_00_2.v:28: error: invalid module item.

test_10_03_00_2.v:30: syntax error

test_10_03_00_2.v:30: error: invalid module item.

test_10_03_00_2.v:31: syntax error

</pre>

# test_10_03_00_3.v

<pre>

test_10_03_00_3.v:30: error: Unable to bind wire/reg/memory `a' in `test.proc_a'

test_10_03_00_3.v:30: error: Unable to elaborate condition expression.

</pre>

# test_10_03_00_4.v

<pre>

test_10_03_00_4.v:34: syntax error

test_10_03_00_4.v:35: error: invalid module item.

test_10_03_00_4.v:35: syntax error

test_10_03_00_4.v:35: error: Invalid module instantiation

test_10_03_00_4.v:35: error: Invalid module instantiation

test_10_03_00_4.v:39: error: Invalid module instantiation

test_10_03_00_4.v:40: error: Invalid module instantiation

test_10_03_00_4.v:43: error: invalid module item.

test_10_03_00_4.v:44: syntax error

test_10_03_00_4.v:44: error: Invalid module instantiation

test_10_03_00_4.v:45: error: Invalid module instantiation

</pre>

# test_10_03_00_5.v

<pre>

test_10_03_00_5.v:28: syntax error

</pre>

# test_10_04_05_1.v

<pre>

test_10_04_05_1.v:27: sorry: constant user functions are not currently supported: clogb2().

</pre>

# test_11_05_00_1.v

<pre>

test_11_05_00_1.v:29: error: reg p; cannot be driven by primitives or continuous assignment.

</pre>

# test_12_02_00_1.v

<pre>

test_12_02_00_1.v:54: syntax error

</pre>

# test_12_02_00_2.v

<pre>

test_12_02_00_2.v:28: error: Port a (1) of module foo is not declared within module.

test_12_02_00_2.v:28: error: Port b (2) of module foo is not declared within module.

test_12_02_00_2.v:28: error: no wire/reg a in module bar.f1.

test_12_02_00_2.v:28: error: no wire/reg b in module bar.f1.

</pre>

# test_12_02_01_1.v

<pre>

test_12_02_01_1.v:29: syntax error

</pre>

# test_12_02_02_1_2.v

<pre>

test_12_02_02_1_2.v:28: error: Port addr (1) of module my_mem is not declared within module.

test_12_02_02_1_2.v:28: error: Port data (2) of module my_mem is not declared within module.

test_12_02_02_1_2.v:28: error: no wire/reg addr in module top.m.

test_12_02_02_1_2.v:28: error: no wire/reg data in module top.m.

</pre>

# test_12_03_03_2.v

<pre>

test_12_03_03_2.v:46: syntax error

test_12_03_03_2.v:46: error: missing endmodule or attempt to nest modules.

test_12_03_03_2.v:40: error: original module (complex_ports) defined here.

test_12_03_03_2.v:52: syntax error

test_12_03_03_2.v:52: error: missing endmodule or attempt to nest modules.

test_12_03_03_2.v:40: error: original module (complex_ports) defined here.

test_12_03_03_2.v:56: syntax error

test_12_03_03_2.v:56: error: missing endmodule or attempt to nest modules.

test_12_03_03_2.v:40: error: original module (complex_ports) defined here.

test_12_03_03_2.v:61: syntax error

test_12_03_03_2.v:61: error: missing endmodule or attempt to nest modules.

test_12_03_03_2.v:40: error: original module (complex_ports) defined here.

test_12_03_03_2.v:65: syntax error

test_12_03_03_2.v:65: error: missing endmodule or attempt to nest modules.

test_12_03_03_2.v:40: error: original module (complex_ports) defined here.

test_12_03_03_2.v:66: error: port a already has a port declaration.

test_12_03_03_2.v:62: error: Port ``a'' has already been declared a port.

</pre>

# test_12_03_06_1.v

<pre>

test_12_03_06_1.v:34: error: port ``Out'' is not a port of instance1.

test_12_03_06_1.v:34: error: port ``In1'' is not a port of instance1.

test_12_03_06_1.v:34: error: port ``In2'' is not a port of instance1.

</pre>

# test_12_03_07_1.v

<pre>

test_12_03_07_1.v:29: error: Scalar port ``net_r'' has a vectored net declaration [64:1].

test_12_03_07_1.v:34: error: Scalar port ``net_r'' has a vectored net declaration [64:1].

test_12_03_07_1.v:36: error: Unable to bind wire/reg/memory `net_r' in `receiver'

ivl: netmisc.cc:467: void eval_expr(NetExpr*&, int): Assertion `expr' failed.

</pre>

# test_12_04_01_1.v

<pre>

test_12_04_01_1.v:49: syntax error

</pre>

# test_12_04_01_2.v

<pre>

test_12_04_01_2.v:39: syntax error

</pre>

# test_12_04_01_5.v

<pre>

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:33: error: Unknown module type: M2

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:33: error: Unknown module type: M2

test_12_04_01_5.v:31: error: Unknown module type: M1

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:33: error: Unknown module type: M2

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:35: error: Unknown module type: M3

test_12_04_01_5.v:33: error: Unknown module type: M2

test_12_04_01_5.v:40: error: Unknown module type: M4

test_12_04_01_5.v:40: error: Unknown module type: M4

test_12_04_01_5.v:31: error: Unknown module type: M1

*** These modules were missing:

        M1 referenced 2 times.

        M2 referenced 4 times.

        M3 referenced 8 times.

        M4 referenced 2 times.

***

</pre>

# test_12_04_02_1.v

<pre>

test_12_04_02_1.v:46: syntax error

test_12_04_02_1.v:46: error: invalid module item.

</pre>

# test_12_04_02_2.v

<pre>

test_12_04_02_2.v:44: error: Wrong number of ports. Expecting 0, got 3.

</pre>

# test_12_04_02_3.v

<pre>

test_12_04_02_3.v:26: error: Cannot evaluate genvar case expression: WIDTH

</pre>

# test_12_04_02_4.v

<pre>

test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0

test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0

test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0

test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0

*** These modules were missing:

        sms_08b216t0 referenced 4 times.

***

</pre>

# test_12_06_00_1.v

<pre>

test_12_06_00_1.v:34: error: Could not find variable ``b_c1.i'' in ``a._b1''

test_12_06_00_1.v:34: error: Could not find variable ``b_c1.i'' in ``d.d_b1''

test_12_06_00_1.v:53: error: Could not find variable ``a.a_b1.i'' in ``d''

test_12_06_00_1.v:55: error: Could not find variable ``a.a_b1.b_c1.i'' in ``d''

test_12_06_00_1.v:56: error: Could not find variable ``d.d_b1.b_c1.i'' in ``d''

test_12_06_00_1.v:57: error: Could not find variable ``a.a_b1.b_c2.i'' in ``d''

</pre>