Project

General

Profile

Icarus Verilog Bugs » History » Version 4

Sergey Smolov, 04/27/2018 06:43 PM

1 1 Sergey Smolov
h1. Icarus Verilog Bugs
2
3
The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests"). 
4
5
# test_03_08_01_1.v
6
<pre>
7
test_03_08_01_1.v:25: syntax error
8
test_03_08_01_1.v:27: error: malformed statement
9
test_03_08_01_1.v:28: syntax error
10
test_03_08_01_1.v:33: error: malformed statement
11
test_03_08_01_1.v:34: syntax error
12
test_03_08_01_1.v:39: error: malformed statement
13
test_03_08_01_1.v:40: syntax error
14
</pre>
15 4 Sergey Smolov
*Cause*: attributes for "case" statement branches like "(* full_case, parallel_case *)" are unsupported.
16 2 Sergey Smolov
# test_03_08_01_2.v
17
<pre>
18
test_03_08_01_2.v:25: syntax error
19
test_03_08_01_2.v:27: error: malformed statement
20
test_03_08_01_2.v:28: syntax error
21
test_03_08_01_2.v:32: error: malformed statement
22
test_03_08_01_2.v:33: syntax error
23
</pre>
24 4 Sergey Smolov
*Cause*: attributes for "case" statement branches like "(* full_case *)" are unsupported.
25 3 Sergey Smolov
# test_03_08_01_6.v
26
<pre>
27
test_03_08_01_6.v:25: syntax error
28
test_03_08_01_6.v:25: error: malformed statement
29
</pre>
30 4 Sergey Smolov
*Cause*: attributes for assignments like "a = b + (* mode = "cla" *) c;" are unsupported.
31 1 Sergey Smolov
# test_03_08_01_7.v
32
<pre>
33
test_03_08_01_7.v:25: syntax error
34
test_03_08_01_7.v:25: error: malformed statement
35
</pre>
36 4 Sergey Smolov
*Cause*: attributes for assignments like "a = add (* mode = "cla" *) (b, c);" are unsupported.
37 3 Sergey Smolov
# test_03_08_01_8.v
38
<pre>
39
test_03_08_01_8.v:25: syntax error
40
test_03_08_01_8.v:25: error: malformed statement
41
</pre>
42 4 Sergey Smolov
*Cause*: attributes for assignments like "a = b ? (* no_glitch *) c : d;" are unsupported.
43 1 Sergey Smolov
# test_04_03_01_1.v
44
<pre>
45
test_04_03_01_1.v:24: sorry: trireg nets not supported.
46
</pre>
47 4 Sergey Smolov
*Cause*: cannot parse "trireg (small) storeit;"
48 1 Sergey Smolov
# test_04_03_02_1.v
49
<pre>
50
test_04_03_02_1.v:22: syntax error
51
test_04_03_02_1.v:22: error: invalid module item.
52
test_04_03_02_1.v:23: syntax error
53
test_04_03_02_1.v:23: error: invalid module item.
54
</pre>
55 4 Sergey Smolov
*Cause*: cannot parse "tri1 scalared [63:0] bus64;"
56 1 Sergey Smolov
# test_04_04_01_1.v
57
<pre>
58
test_04_04_01_1.v:22: sorry: trireg nets not supported.
59
test_04_04_01_1.v:23: sorry: trireg nets not supported.
60
test_04_04_01_1.v:25: syntax error
61
test_04_04_01_1.v:25: error: invalid module item.
62
</pre>
63 4 Sergey Smolov
*Cause*: cannot parse "trireg a;"
64 3 Sergey Smolov
# test_04_09_03_1_1.v
65
<pre>
66
test_04_09_03_1_1.v:26: sorry: only 1 dimensional arrays are currently supported.
67
test_04_09_03_1_1.v:28: sorry: only 1 dimensional arrays are currently supported.
68
</pre>
69 4 Sergey Smolov
*Cause*: cannot parse "reg arrayb[7:0][0:255];"
70 3 Sergey Smolov
# test_04_09_03_1_2.v
71
<pre>
72
test_04_09_03_1_2.v:26: sorry: only 1 dimensional arrays are currently supported.
73
test_04_09_03_1_2.v:28: sorry: only 1 dimensional arrays are currently supported.
74
</pre>
75 4 Sergey Smolov
*Cause*: cannot parse "reg arrayb[7:0][0:255];"
76 3 Sergey Smolov
# test_04_10_03_2.v
77
<pre>
78
test_04_10_03_2.v:23: syntax error
79
test_04_10_03_2.v:23: error: invalid module item.
80
test_04_10_03_2.v:24: syntax error
81
test_04_10_03_2.v:24: error: invalid module item.
82
</pre>
83 4 Sergey Smolov
*Cause*: the "specparam" is unsupported.
84 3 Sergey Smolov
# test_05_01_14_1.v
85
<pre>
86
test_05_01_14_1.v:30: error: Array b['sd3:'sd0] cannot be indexed by a range.
87
</pre>
88 4 Sergey Smolov
*Cause*: cannot parse "result = {a, b[3:0], w, 3'b101};"
89 1 Sergey Smolov
# test_05_02_01_4.v
90
<pre>
91
test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'
92
test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'
93
</pre>
94 4 Sergey Smolov
*Cause*: cannot parse "addr = x;"
95 3 Sergey Smolov
# test_05_02_02_2.v
96
<pre>
97
test_05_02_02_2.v:25: sorry: only 1 dimensional arrays are currently supported.
98
test_05_02_02_2.v:26: sorry: only 1 dimensional arrays are currently supported.
99
</pre>
100 4 Sergey Smolov
*Cause*: cnnot parse "wire threed_array[0:255][0:255][0:7];"
101 1 Sergey Smolov
# test_05_03_00_1.v
102
<pre>
103
test_05_03_00_1.v:25: warning: choosing typ expression.
104
</pre>
105 4 Sergey Smolov
*Cause*: "parameter val = (32'd 50: 32'd 75: 32'd 100);"
106 1 Sergey Smolov
# test_06_01_03_1.v
107
<pre>
108
test_06_01_03_1.v:24: sorry: net delays not supported.
109
</pre>
110 4 Sergey Smolov
*Cause*: "wire #10 wireA;"
111 3 Sergey Smolov
# test_07_14_01_1.v
112 1 Sergey Smolov
<pre>
113
test_07_14_01_1.v:25: warning: choosing typ expression.
114
test_07_14_01_1.v:25: warning: choosing typ expression.
115
test_07_14_01_1.v:25: warning: choosing typ expression.
116
test_07_14_01_1.v:26: warning: choosing typ expression.
117
test_07_14_01_1.v:26: warning: choosing typ expression.
118
test_07_14_01_1.v:26: warning: choosing typ expression.
119
</pre>
120
# test_07_14_01_2.v
121
<pre>
122
test_07_14_01_2.v:26: warning: choosing typ expression.
123
test_07_14_01_2.v:27: warning: choosing typ expression.
124
</pre>
125
# test_07_14_02_2_1.v
126
<pre>
127
test_07_14_02_2_1.v:25: sorry: trireg nets not supported.
128
</pre>
129
# test_07_14_02_2_2.v
130
<pre>
131
test_07_14_02_2_2.v:26: sorry: trireg nets not supported.
132
</pre>
133
# test_08_06_00_1.v
134
<pre>
135
test_08_06_00_1.v:46: syntax error
136
test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.
137
test_08_06_00_1.v:46: error: Invalid module instantiation
138
</pre>
139 3 Sergey Smolov
# test_08_07_00_1.v
140
<pre>
141
test_08_07_00_1.v:30: syntax error
142
</pre>
143 1 Sergey Smolov
# test_09_02_01_1.v
144
<pre>
145
test_09_02_01_1.v:31: error: part select rega[3:5] is reversed.
146
</pre>
147 3 Sergey Smolov
# test_09_06_00_1.v
148 1 Sergey Smolov
<pre>
149 3 Sergey Smolov
test_09_06_00_1.v:27: syntax error
150
test_09_06_00_1.v:28: error: invalid module item.
151
test_09_06_00_1.v:29: syntax error
152
test_09_06_00_1.v:29: error: Invalid module instantiation
153
test_09_06_00_1.v:30: error: Invalid module instantiation
154
test_09_06_00_1.v:31: error: Invalid module instantiation
155
test_09_06_00_1.v:34: error: invalid module item.
156
test_09_06_00_1.v:35: syntax error
157
test_09_06_00_1.v:35: error: Invalid module instantiation
158
test_09_06_00_1.v:36: error: Invalid module instantiation
159 1 Sergey Smolov
</pre>
160 3 Sergey Smolov
# test_09_06_00_2.v
161 1 Sergey Smolov
<pre>
162 3 Sergey Smolov
test_09_06_00_2.v:23: syntax error
163
test_09_06_00_2.v:24: error: invalid module item.
164
test_09_06_00_2.v:25: syntax error
165
test_09_06_00_2.v:25: error: Invalid module instantiation
166
test_09_06_00_2.v:26: error: Invalid module instantiation
167
test_09_06_00_2.v:29: error: invalid module item.
168
test_09_06_00_2.v:30: syntax error
169
test_09_06_00_2.v:30: error: Invalid module instantiation
170
</pre>
171
# test_09_06_00_3.v
172
<pre>
173
test_09_06_00_3.v:27: syntax error
174
test_09_06_00_3.v:27: Syntax in assignment statement l-value.
175
test_09_06_00_3.v:28: syntax error
176
test_09_06_00_3.v:28: Syntax in assignment statement l-value.
177
test_09_06_00_3.v:35: syntax error
178
test_09_06_00_3.v:35: error: Incomprehensible for loop.
179
</pre>
180
# test_09_07_01_2.v
181
<pre> 
182
test_09_07_01_2.v:30: syntax error
183
test_09_07_01_2.v:30: Syntax in assignment statement l-value.
184
</pre>
185
# test_09_07_05_1.v 
186
<pre>
187
test_09_07_05_1.v:31: syntax error
188
</pre>
189
# test_09_07_05_2.v 
190
<pre>
191
test_09_07_05_2.v:30: error: port y already has a port declaration.
192
test_09_07_05_2.v:29: error: Port ``y'' has already been declared a port.
193
</pre>
194
# test_09_07_05_3.v 
195
<pre>
196
test_09_07_05_3.v:32: internal error: NetProc::nex_input not implemented
197
test_09_07_05_3.v:31: error: Unable to elaborate:
198
      @(test._s0)  // test_09_07_05_3.v:32
199
        {kid} = b[0:0];
200
</pre>
201
# test_09_07_05_4.v 
202
<pre>
203
test_09_07_05_4.v:33: internal error: NetProc::nex_input not implemented
204
</pre>
205
# test_09_07_05_5.v 
206
<pre>
207
test_09_07_05_5.v:32: error: y is not a valid l-value in test.
208
test_09_07_05_5.v:29:      : y is declared here as wire.
209
test_09_07_05_5.v:33: error: y[a] is not a valid l-value in test.
210
test_09_07_05_5.v:29:      : y[a] is declared here as wire.
211
test_09_07_05_5.v:31: warning: @* found no sensitivities so it will never trigger.
212
</pre>
213
# test_09_07_05_6.v
214
<pre>
215
test_09_07_05_6.v:35: error: Unable to bind wire/reg/memory `IDLE' in `test'
216
test_09_07_05_6.v:35: error: Unable to bind wire/reg/memory `READ' in `test'
217
test_09_07_05_6.v:36: error: Unable to bind wire/reg/memory `IDLE' in `test'
218
test_09_07_05_6.v:37: error: Unable to bind wire/reg/memory `READ' in `test'
219
test_09_07_05_6.v:37: error: Unable to bind wire/reg/memory `DLY' in `test'
220
test_09_07_05_6.v:38: error: Unable to bind wire/reg/memory `DLY' in `test'
221
test_09_07_05_6.v:38: error: Unable to bind wire/reg/memory `DONE' in `test'
222
</pre>
223
# test_09_07_06_1.v
224
<pre>
225
test_09_07_06_1.v:32: syntax error
226
test_09_07_06_1.v:33: error: invalid module item.
227
test_09_07_06_1.v:34: syntax error
228
test_09_07_06_1.v:34: error: invalid module item.
229
test_09_07_06_1.v:35: syntax error
230
</pre>
231
# test_09_07_07_1.v
232
<pre>
233
test_09_07_07_1.v:32: syntax error
234
</pre>
235
# test_09_07_07_3.v
236
<pre>
237
test_09_07_07_3.v:28: error: Unable to bind wire/reg/memory `clk' in `test'
238
test_09_07_07_3.v:33: error: Unable to bind wire/reg/memory `clk' in `test'
239
</pre>
240
# test_09_07_07_4.v
241
<pre>
242
test_09_07_07_4.v:29: error: Unable to bind wire/reg/memory `clk' in `test'
243
test_09_07_07_4.v:34: error: Unable to bind wire/reg/memory `clk' in `test'
244
test_09_07_07_4.v:35: error: Unable to bind wire/reg/memory `clk' in `test'
245
test_09_07_07_4.v:36: error: Unable to bind wire/reg/memory `clk' in `test'
246
</pre>
247
# test_09_07_07_9.v
248
<pre>
249
test_09_07_07_9.v:31: error: Unable to bind wire/reg/memory `data' in `test'
250
</pre>
251
# test_09_08_01_3.v 
252
<pre>
253
test_09_08_01_3.v:33: error: event <end_wave> not found.
254
</pre>
255
# test_09_08_02_1.v 
256
<pre>
257
test_09_08_02_1.v:35: error: event <end_wave> not found.
258
</pre>
259
# test_09_08_04_1.v 
260
<pre>
261
test_09_08_04_1.v:29: error: event <end_wave> not found.
262
</pre>
263
# test_09_08_04_2.v 
264
<pre>
265
:0: error: Unable to bind wire/reg/memory `Aevent' in `test'
266
:0: error: Unable to bind wire/reg/memory `Bevent' in `test'
267
</pre>
268
# test_09_08_04_3.v 
269
<pre>
270
:0: error: Unable to bind wire/reg/memory `enable_a' in `test'
271
:0: error: Unable to bind wire/reg/memory `enable_b' in `test'
272
</pre>
273
# test_09_09_01_1.v 
274
<pre>
275
test_09_09_01_1.v:27: error: signal and parameter in 'test' have the same name 'size'.
276
</pre>
277
# test_09_09_02_1.v 
278
<pre>
279
test_09_09_02_1.v:26: error: always statement does not have any delay.
280
test_09_09_02_1.v:26:      : A runtime infinite loop will occur.
281
</pre>
282
# test_10_01_00_1.v 
283
<pre>
284
test_10_01_00_1.v:29: syntax error
285
test_10_01_00_1.v:32: error: malformed statement
286
test_10_01_00_1.v:33: syntax error
287
</pre>
288
# test_10_01_00_2.v 
289
<pre>
290
test_10_01_00_2.v:27: syntax error
291
test_10_01_00_2.v:30: Syntax in assignment statement l-value.
292
test_10_01_00_2.v:31: syntax error
293
</pre>
294
# test_10_02_02_1_1.v 
295
<pre>
296
test_10_02_02_1_1.v:31: error: Could not find variable ``foo1'' in ``test.my_task''
297
test_10_02_02_1_1.v:32: error: Could not find variable ``foo1'' in ``test.my_task''
298
test_10_02_02_1_1.v:33: error: Could not find variable ``foo1'' in ``test.my_task''
299
test_10_02_02_1_1.v:34: error: Could not find variable ``foo1'' in ``test.my_task''
300
test_10_02_02_1_1.v:35: error: Unable to bind wire/reg/memory `foo1' in `test.my_task'
301
test_10_02_02_1_1.v:36: error: Unable to bind wire/reg/memory `foo2' in `test.my_task'
302
test_10_02_02_1_1.v:37: error: Unable to bind wire/reg/memory `foo3' in `test.my_task'
303
</pre>
304
# test_10_02_02_1_2.v 
305
<pre>
306
test_10_02_02_1_2.v:27: error: Could not find variable ``foo1'' in ``test.my_task''
307
test_10_02_02_1_2.v:28: error: Could not find variable ``foo2'' in ``test.my_task''
308
test_10_02_02_1_2.v:29: error: Could not find variable ``foo3'' in ``test.my_task''
309
test_10_02_02_1_2.v:30: error: Unable to bind wire/reg/memory `foo1' in `test.my_task'
310
test_10_02_02_1_2.v:31: error: Unable to bind wire/reg/memory `foo2' in `test.my_task'
311
test_10_02_02_1_2.v:32: error: Unable to bind wire/reg/memory `foo3' in `test.my_task'
312
</pre>
313
# test_10_03_00_1.v 
314
<pre>
315
test_10_03_00_1.v:25: syntax error
316
test_10_03_00_1.v:26: error: invalid module item.
317
test_10_03_00_1.v:27: syntax error
318
test_10_03_00_1.v:27: error: invalid module item.
319
test_10_03_00_1.v:28: syntax error
320
test_10_03_00_1.v:28: error: Invalid module instantiation
321
</pre>
322
# test_10_03_00_2.v 
323
<pre>
324
test_10_03_00_2.v:27: syntax error
325
test_10_03_00_2.v:28: error: invalid module item.
326
test_10_03_00_2.v:30: syntax error
327
test_10_03_00_2.v:30: error: invalid module item.
328
test_10_03_00_2.v:31: syntax error
329
</pre>
330
# test_10_03_00_3.v 
331
<pre>
332
test_10_03_00_3.v:30: error: Unable to bind wire/reg/memory `a' in `test.proc_a'
333
test_10_03_00_3.v:30: error: Unable to elaborate condition expression.
334
</pre>
335
# test_10_03_00_4.v 
336
<pre>
337
test_10_03_00_4.v:34: syntax error
338
test_10_03_00_4.v:35: error: invalid module item.
339
test_10_03_00_4.v:35: syntax error
340
test_10_03_00_4.v:35: error: Invalid module instantiation
341
test_10_03_00_4.v:35: error: Invalid module instantiation
342
test_10_03_00_4.v:39: error: Invalid module instantiation
343
test_10_03_00_4.v:40: error: Invalid module instantiation
344
test_10_03_00_4.v:43: error: invalid module item.
345
test_10_03_00_4.v:44: syntax error
346
test_10_03_00_4.v:44: error: Invalid module instantiation
347
test_10_03_00_4.v:45: error: Invalid module instantiation
348
</pre>
349
# test_10_03_00_5.v 
350
<pre>
351
test_10_03_00_5.v:28: syntax error
352
</pre>
353
# test_10_04_05_1.v 
354
<pre>
355
test_10_04_05_1.v:27: sorry: constant user functions are not currently supported: clogb2().
356
</pre>
357
# test_11_05_00_1.v 
358
<pre>
359
test_11_05_00_1.v:29: error: reg p; cannot be driven by primitives or continuous assignment.
360
</pre>
361
# test_12_02_00_1.v 
362
<pre>
363
test_12_02_00_1.v:54: syntax error
364
</pre>
365
# test_12_02_00_2.v 
366
<pre>
367
test_12_02_00_2.v:28: error: Port a (1) of module foo is not declared within module.
368
test_12_02_00_2.v:28: error: Port b (2) of module foo is not declared within module.
369
test_12_02_00_2.v:28: error: no wire/reg a in module bar.f1.
370
test_12_02_00_2.v:28: error: no wire/reg b in module bar.f1.
371
</pre>
372
# test_12_02_01_1.v 
373
<pre>
374
test_12_02_01_1.v:29: syntax error
375
</pre>
376
# test_12_02_02_1_2.v 
377
<pre>
378
test_12_02_02_1_2.v:28: error: Port addr (1) of module my_mem is not declared within module.
379
test_12_02_02_1_2.v:28: error: Port data (2) of module my_mem is not declared within module.
380
test_12_02_02_1_2.v:28: error: no wire/reg addr in module top.m.
381
test_12_02_02_1_2.v:28: error: no wire/reg data in module top.m.
382
</pre>
383
# test_12_03_03_2.v 
384
<pre>
385
test_12_03_03_2.v:46: syntax error
386
test_12_03_03_2.v:46: error: missing endmodule or attempt to nest modules.
387
test_12_03_03_2.v:40: error: original module (complex_ports) defined here.
388
test_12_03_03_2.v:52: syntax error
389
test_12_03_03_2.v:52: error: missing endmodule or attempt to nest modules.
390
test_12_03_03_2.v:40: error: original module (complex_ports) defined here.
391
test_12_03_03_2.v:56: syntax error
392
test_12_03_03_2.v:56: error: missing endmodule or attempt to nest modules.
393
test_12_03_03_2.v:40: error: original module (complex_ports) defined here.
394
test_12_03_03_2.v:61: syntax error
395
test_12_03_03_2.v:61: error: missing endmodule or attempt to nest modules.
396
test_12_03_03_2.v:40: error: original module (complex_ports) defined here.
397
test_12_03_03_2.v:65: syntax error
398
test_12_03_03_2.v:65: error: missing endmodule or attempt to nest modules.
399
test_12_03_03_2.v:40: error: original module (complex_ports) defined here.
400
test_12_03_03_2.v:66: error: port a already has a port declaration.
401
test_12_03_03_2.v:62: error: Port ``a'' has already been declared a port.
402
</pre>
403
# test_12_03_06_1.v 
404
<pre>
405
test_12_03_06_1.v:34: error: port ``Out'' is not a port of instance1.
406
test_12_03_06_1.v:34: error: port ``In1'' is not a port of instance1.
407
test_12_03_06_1.v:34: error: port ``In2'' is not a port of instance1.
408
</pre>
409
# test_12_03_07_1.v 
410
<pre>
411
test_12_03_07_1.v:29: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
412
test_12_03_07_1.v:34: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
413
test_12_03_07_1.v:36: error: Unable to bind wire/reg/memory `net_r' in `receiver'
414
ivl: netmisc.cc:467: void eval_expr(NetExpr*&, int): Assertion `expr' failed.
415
</pre>
416
# test_12_04_01_1.v 
417
<pre>
418
test_12_04_01_1.v:49: syntax error
419
</pre>
420
# test_12_04_01_2.v 
421
<pre>
422
test_12_04_01_2.v:39: syntax error
423
</pre>
424
# test_12_04_01_5.v 
425
<pre>
426
test_12_04_01_5.v:35: error: Unknown module type: M3
427
test_12_04_01_5.v:35: error: Unknown module type: M3
428
test_12_04_01_5.v:33: error: Unknown module type: M2
429
test_12_04_01_5.v:35: error: Unknown module type: M3
430
test_12_04_01_5.v:35: error: Unknown module type: M3
431
test_12_04_01_5.v:33: error: Unknown module type: M2
432
test_12_04_01_5.v:31: error: Unknown module type: M1
433
test_12_04_01_5.v:35: error: Unknown module type: M3
434
test_12_04_01_5.v:35: error: Unknown module type: M3
435
test_12_04_01_5.v:33: error: Unknown module type: M2
436
test_12_04_01_5.v:35: error: Unknown module type: M3
437
test_12_04_01_5.v:35: error: Unknown module type: M3
438
test_12_04_01_5.v:33: error: Unknown module type: M2
439
test_12_04_01_5.v:40: error: Unknown module type: M4
440
test_12_04_01_5.v:40: error: Unknown module type: M4
441
test_12_04_01_5.v:31: error: Unknown module type: M1
442
*** These modules were missing:
443
        M1 referenced 2 times.
444
        M2 referenced 4 times.
445
        M3 referenced 8 times.
446
        M4 referenced 2 times.
447
***
448
</pre>
449
# test_12_04_02_1.v 
450
<pre>
451
test_12_04_02_1.v:46: syntax error
452
test_12_04_02_1.v:46: error: invalid module item.
453
</pre>
454
# test_12_04_02_2.v 
455
<pre>
456
test_12_04_02_2.v:44: error: Wrong number of ports. Expecting 0, got 3.
457
</pre>
458
# test_12_04_02_3.v 
459
<pre>
460
test_12_04_02_3.v:26: error: Cannot evaluate genvar case expression: WIDTH
461
</pre>
462
# test_12_04_02_4.v 
463
<pre>
464
test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0
465
test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0
466
test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0
467
test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0
468
*** These modules were missing:
469
        sms_08b216t0 referenced 4 times.
470
***
471
</pre>
472
473
# test_12_06_00_1.v 
474
<pre>
475
test_12_06_00_1.v:34: error: Could not find variable ``b_c1.i'' in ``a._b1''
476
test_12_06_00_1.v:34: error: Could not find variable ``b_c1.i'' in ``d.d_b1''
477
test_12_06_00_1.v:53: error: Could not find variable ``a.a_b1.i'' in ``d''
478
test_12_06_00_1.v:55: error: Could not find variable ``a.a_b1.b_c1.i'' in ``d''
479
test_12_06_00_1.v:56: error: Could not find variable ``d.d_b1.b_c1.i'' in ``d''
480
test_12_06_00_1.v:57: error: Could not find variable ``a.a_b1.b_c2.i'' in ``d''
481 1 Sergey Smolov
</pre>