Icarus Verilog Bugs » History » Version 3
Sergey Smolov, 04/27/2018 05:32 PM
1 | 1 | Sergey Smolov | h1. Icarus Verilog Bugs |
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3 | The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests"). |
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4 | |||
5 | # test_03_08_01_1.v |
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6 | <pre> |
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7 | test_03_08_01_1.v:25: syntax error |
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8 | test_03_08_01_1.v:27: error: malformed statement |
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9 | test_03_08_01_1.v:28: syntax error |
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10 | test_03_08_01_1.v:33: error: malformed statement |
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11 | test_03_08_01_1.v:34: syntax error |
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12 | test_03_08_01_1.v:39: error: malformed statement |
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13 | test_03_08_01_1.v:40: syntax error |
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14 | </pre> |
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15 | 2 | Sergey Smolov | # test_03_08_01_2.v |
16 | <pre> |
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17 | test_03_08_01_2.v:25: syntax error |
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18 | test_03_08_01_2.v:27: error: malformed statement |
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19 | test_03_08_01_2.v:28: syntax error |
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20 | test_03_08_01_2.v:32: error: malformed statement |
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21 | test_03_08_01_2.v:33: syntax error |
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22 | </pre> |
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23 | 3 | Sergey Smolov | # test_03_08_01_6.v |
24 | <pre> |
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25 | test_03_08_01_6.v:25: syntax error |
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26 | test_03_08_01_6.v:25: error: malformed statement |
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27 | </pre> |
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28 | 1 | Sergey Smolov | # test_03_08_01_7.v |
29 | <pre> |
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30 | test_03_08_01_7.v:25: syntax error |
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31 | test_03_08_01_7.v:25: error: malformed statement |
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32 | </pre> |
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33 | 3 | Sergey Smolov | # test_03_08_01_8.v |
34 | <pre> |
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35 | test_03_08_01_8.v:25: syntax error |
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36 | test_03_08_01_8.v:25: error: malformed statement |
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37 | </pre> |
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38 | 1 | Sergey Smolov | # test_04_03_01_1.v |
39 | <pre> |
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40 | test_04_03_01_1.v:24: sorry: trireg nets not supported. |
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41 | </pre> |
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42 | # test_04_03_02_1.v |
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43 | <pre> |
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44 | test_04_03_02_1.v:22: syntax error |
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45 | test_04_03_02_1.v:22: error: invalid module item. |
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46 | test_04_03_02_1.v:23: syntax error |
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47 | test_04_03_02_1.v:23: error: invalid module item. |
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48 | </pre> |
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49 | # test_04_04_01_1.v |
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50 | <pre> |
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51 | test_04_04_01_1.v:22: sorry: trireg nets not supported. |
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52 | test_04_04_01_1.v:23: sorry: trireg nets not supported. |
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53 | test_04_04_01_1.v:25: syntax error |
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54 | test_04_04_01_1.v:25: error: invalid module item. |
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55 | </pre> |
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56 | 3 | Sergey Smolov | # test_04_09_03_1_1.v |
57 | <pre> |
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58 | test_04_09_03_1_1.v:26: sorry: only 1 dimensional arrays are currently supported. |
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59 | test_04_09_03_1_1.v:28: sorry: only 1 dimensional arrays are currently supported. |
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60 | </pre> |
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61 | # test_04_09_03_1_2.v |
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62 | <pre> |
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63 | test_04_09_03_1_2.v:26: sorry: only 1 dimensional arrays are currently supported. |
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64 | test_04_09_03_1_2.v:28: sorry: only 1 dimensional arrays are currently supported. |
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65 | </pre> |
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66 | # test_04_10_03_2.v |
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67 | <pre> |
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68 | test_04_10_03_2.v:23: syntax error |
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69 | test_04_10_03_2.v:23: error: invalid module item. |
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70 | test_04_10_03_2.v:24: syntax error |
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71 | test_04_10_03_2.v:24: error: invalid module item. |
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72 | </pre> |
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73 | # test_05_01_14_1.v |
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74 | <pre> |
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75 | test_05_01_14_1.v:30: error: Array b['sd3:'sd0] cannot be indexed by a range. |
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76 | </pre> |
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77 | 1 | Sergey Smolov | # test_05_02_01_4.v |
78 | <pre> |
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79 | test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test' |
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80 | test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test' |
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81 | </pre> |
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82 | 3 | Sergey Smolov | # test_05_02_02_2.v |
83 | <pre> |
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84 | test_05_02_02_2.v:25: sorry: only 1 dimensional arrays are currently supported. |
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85 | test_05_02_02_2.v:26: sorry: only 1 dimensional arrays are currently supported. |
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86 | </pre> |
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87 | 1 | Sergey Smolov | # test_05_03_00_1.v |
88 | <pre> |
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89 | test_05_03_00_1.v:25: warning: choosing typ expression. |
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90 | </pre> |
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91 | # test_06_01_03_1.v |
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92 | <pre> |
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93 | test_06_01_03_1.v:24: sorry: net delays not supported. |
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94 | </pre> |
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95 | 3 | Sergey Smolov | # test_07_14_01_1.v |
96 | 1 | Sergey Smolov | <pre> |
97 | test_07_14_01_1.v:25: warning: choosing typ expression. |
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98 | test_07_14_01_1.v:25: warning: choosing typ expression. |
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99 | test_07_14_01_1.v:25: warning: choosing typ expression. |
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100 | test_07_14_01_1.v:26: warning: choosing typ expression. |
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101 | test_07_14_01_1.v:26: warning: choosing typ expression. |
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102 | test_07_14_01_1.v:26: warning: choosing typ expression. |
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103 | </pre> |
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104 | # test_07_14_01_2.v |
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105 | <pre> |
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106 | test_07_14_01_2.v:26: warning: choosing typ expression. |
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107 | test_07_14_01_2.v:27: warning: choosing typ expression. |
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108 | </pre> |
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109 | # test_07_14_02_2_1.v |
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110 | <pre> |
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111 | test_07_14_02_2_1.v:25: sorry: trireg nets not supported. |
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112 | </pre> |
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113 | # test_07_14_02_2_2.v |
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114 | <pre> |
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115 | test_07_14_02_2_2.v:26: sorry: trireg nets not supported. |
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116 | </pre> |
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117 | # test_08_06_00_1.v |
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118 | <pre> |
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119 | test_08_06_00_1.v:46: syntax error |
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120 | test_08_06_00_1.v:46: error: syntax error in parameter value assignment list. |
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121 | test_08_06_00_1.v:46: error: Invalid module instantiation |
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122 | </pre> |
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123 | 3 | Sergey Smolov | # test_08_07_00_1.v |
124 | <pre> |
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125 | test_08_07_00_1.v:30: syntax error |
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126 | </pre> |
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127 | 1 | Sergey Smolov | # test_09_02_01_1.v |
128 | <pre> |
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129 | test_09_02_01_1.v:31: error: part select rega[3:5] is reversed. |
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130 | </pre> |
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131 | 3 | Sergey Smolov | # test_09_06_00_1.v |
132 | 1 | Sergey Smolov | <pre> |
133 | 3 | Sergey Smolov | test_09_06_00_1.v:27: syntax error |
134 | test_09_06_00_1.v:28: error: invalid module item. |
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135 | test_09_06_00_1.v:29: syntax error |
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136 | test_09_06_00_1.v:29: error: Invalid module instantiation |
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137 | test_09_06_00_1.v:30: error: Invalid module instantiation |
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138 | test_09_06_00_1.v:31: error: Invalid module instantiation |
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139 | test_09_06_00_1.v:34: error: invalid module item. |
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140 | test_09_06_00_1.v:35: syntax error |
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141 | test_09_06_00_1.v:35: error: Invalid module instantiation |
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142 | test_09_06_00_1.v:36: error: Invalid module instantiation |
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143 | 1 | Sergey Smolov | </pre> |
144 | 3 | Sergey Smolov | # test_09_06_00_2.v |
145 | 1 | Sergey Smolov | <pre> |
146 | 3 | Sergey Smolov | test_09_06_00_2.v:23: syntax error |
147 | test_09_06_00_2.v:24: error: invalid module item. |
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148 | test_09_06_00_2.v:25: syntax error |
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149 | test_09_06_00_2.v:25: error: Invalid module instantiation |
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150 | test_09_06_00_2.v:26: error: Invalid module instantiation |
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151 | test_09_06_00_2.v:29: error: invalid module item. |
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152 | test_09_06_00_2.v:30: syntax error |
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153 | test_09_06_00_2.v:30: error: Invalid module instantiation |
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154 | </pre> |
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155 | # test_09_06_00_3.v |
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156 | <pre> |
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157 | test_09_06_00_3.v:27: syntax error |
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158 | test_09_06_00_3.v:27: Syntax in assignment statement l-value. |
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159 | test_09_06_00_3.v:28: syntax error |
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160 | test_09_06_00_3.v:28: Syntax in assignment statement l-value. |
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161 | test_09_06_00_3.v:35: syntax error |
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162 | test_09_06_00_3.v:35: error: Incomprehensible for loop. |
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163 | </pre> |
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164 | # test_09_07_01_2.v |
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165 | <pre> |
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166 | test_09_07_01_2.v:30: syntax error |
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167 | test_09_07_01_2.v:30: Syntax in assignment statement l-value. |
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168 | </pre> |
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169 | # test_09_07_05_1.v |
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170 | <pre> |
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171 | test_09_07_05_1.v:31: syntax error |
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172 | </pre> |
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173 | # test_09_07_05_2.v |
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174 | <pre> |
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175 | test_09_07_05_2.v:30: error: port y already has a port declaration. |
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176 | test_09_07_05_2.v:29: error: Port ``y'' has already been declared a port. |
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177 | </pre> |
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178 | # test_09_07_05_3.v |
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179 | <pre> |
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180 | test_09_07_05_3.v:32: internal error: NetProc::nex_input not implemented |
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181 | test_09_07_05_3.v:31: error: Unable to elaborate: |
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182 | @(test._s0) // test_09_07_05_3.v:32 |
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183 | {kid} = b[0:0]; |
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184 | </pre> |
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185 | # test_09_07_05_4.v |
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186 | <pre> |
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187 | test_09_07_05_4.v:33: internal error: NetProc::nex_input not implemented |
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188 | </pre> |
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189 | # test_09_07_05_5.v |
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190 | <pre> |
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191 | test_09_07_05_5.v:32: error: y is not a valid l-value in test. |
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192 | test_09_07_05_5.v:29: : y is declared here as wire. |
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193 | test_09_07_05_5.v:33: error: y[a] is not a valid l-value in test. |
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194 | test_09_07_05_5.v:29: : y[a] is declared here as wire. |
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195 | test_09_07_05_5.v:31: warning: @* found no sensitivities so it will never trigger. |
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196 | </pre> |
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197 | # test_09_07_05_6.v |
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198 | <pre> |
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199 | test_09_07_05_6.v:35: error: Unable to bind wire/reg/memory `IDLE' in `test' |
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200 | test_09_07_05_6.v:35: error: Unable to bind wire/reg/memory `READ' in `test' |
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201 | test_09_07_05_6.v:36: error: Unable to bind wire/reg/memory `IDLE' in `test' |
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202 | test_09_07_05_6.v:37: error: Unable to bind wire/reg/memory `READ' in `test' |
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203 | test_09_07_05_6.v:37: error: Unable to bind wire/reg/memory `DLY' in `test' |
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204 | test_09_07_05_6.v:38: error: Unable to bind wire/reg/memory `DLY' in `test' |
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205 | test_09_07_05_6.v:38: error: Unable to bind wire/reg/memory `DONE' in `test' |
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206 | </pre> |
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207 | # test_09_07_06_1.v |
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208 | <pre> |
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209 | test_09_07_06_1.v:32: syntax error |
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210 | test_09_07_06_1.v:33: error: invalid module item. |
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211 | test_09_07_06_1.v:34: syntax error |
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212 | test_09_07_06_1.v:34: error: invalid module item. |
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213 | test_09_07_06_1.v:35: syntax error |
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214 | </pre> |
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215 | # test_09_07_07_1.v |
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216 | <pre> |
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217 | test_09_07_07_1.v:32: syntax error |
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218 | </pre> |
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219 | # test_09_07_07_3.v |
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220 | <pre> |
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221 | test_09_07_07_3.v:28: error: Unable to bind wire/reg/memory `clk' in `test' |
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222 | test_09_07_07_3.v:33: error: Unable to bind wire/reg/memory `clk' in `test' |
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223 | </pre> |
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224 | # test_09_07_07_4.v |
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225 | <pre> |
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226 | test_09_07_07_4.v:29: error: Unable to bind wire/reg/memory `clk' in `test' |
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227 | test_09_07_07_4.v:34: error: Unable to bind wire/reg/memory `clk' in `test' |
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228 | test_09_07_07_4.v:35: error: Unable to bind wire/reg/memory `clk' in `test' |
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229 | test_09_07_07_4.v:36: error: Unable to bind wire/reg/memory `clk' in `test' |
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230 | </pre> |
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231 | # test_09_07_07_9.v |
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232 | <pre> |
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233 | test_09_07_07_9.v:31: error: Unable to bind wire/reg/memory `data' in `test' |
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234 | </pre> |
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235 | # test_09_08_01_3.v |
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236 | <pre> |
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237 | test_09_08_01_3.v:33: error: event <end_wave> not found. |
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238 | </pre> |
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239 | # test_09_08_02_1.v |
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240 | <pre> |
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241 | test_09_08_02_1.v:35: error: event <end_wave> not found. |
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242 | </pre> |
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243 | # test_09_08_04_1.v |
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244 | <pre> |
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245 | test_09_08_04_1.v:29: error: event <end_wave> not found. |
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246 | </pre> |
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247 | # test_09_08_04_2.v |
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248 | <pre> |
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249 | :0: error: Unable to bind wire/reg/memory `Aevent' in `test' |
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250 | :0: error: Unable to bind wire/reg/memory `Bevent' in `test' |
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251 | </pre> |
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252 | # test_09_08_04_3.v |
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253 | <pre> |
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254 | :0: error: Unable to bind wire/reg/memory `enable_a' in `test' |
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255 | :0: error: Unable to bind wire/reg/memory `enable_b' in `test' |
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256 | </pre> |
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257 | # test_09_09_01_1.v |
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258 | <pre> |
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259 | test_09_09_01_1.v:27: error: signal and parameter in 'test' have the same name 'size'. |
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260 | </pre> |
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261 | # test_09_09_02_1.v |
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262 | <pre> |
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263 | test_09_09_02_1.v:26: error: always statement does not have any delay. |
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264 | test_09_09_02_1.v:26: : A runtime infinite loop will occur. |
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265 | </pre> |
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266 | # test_10_01_00_1.v |
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267 | <pre> |
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268 | test_10_01_00_1.v:29: syntax error |
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269 | test_10_01_00_1.v:32: error: malformed statement |
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270 | test_10_01_00_1.v:33: syntax error |
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271 | </pre> |
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272 | # test_10_01_00_2.v |
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273 | <pre> |
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274 | test_10_01_00_2.v:27: syntax error |
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275 | test_10_01_00_2.v:30: Syntax in assignment statement l-value. |
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276 | test_10_01_00_2.v:31: syntax error |
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277 | </pre> |
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278 | # test_10_02_02_1_1.v |
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279 | <pre> |
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280 | test_10_02_02_1_1.v:31: error: Could not find variable ``foo1'' in ``test.my_task'' |
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281 | test_10_02_02_1_1.v:32: error: Could not find variable ``foo1'' in ``test.my_task'' |
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282 | test_10_02_02_1_1.v:33: error: Could not find variable ``foo1'' in ``test.my_task'' |
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283 | test_10_02_02_1_1.v:34: error: Could not find variable ``foo1'' in ``test.my_task'' |
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284 | test_10_02_02_1_1.v:35: error: Unable to bind wire/reg/memory `foo1' in `test.my_task' |
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285 | test_10_02_02_1_1.v:36: error: Unable to bind wire/reg/memory `foo2' in `test.my_task' |
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286 | test_10_02_02_1_1.v:37: error: Unable to bind wire/reg/memory `foo3' in `test.my_task' |
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287 | </pre> |
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288 | # test_10_02_02_1_2.v |
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289 | <pre> |
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290 | test_10_02_02_1_2.v:27: error: Could not find variable ``foo1'' in ``test.my_task'' |
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291 | test_10_02_02_1_2.v:28: error: Could not find variable ``foo2'' in ``test.my_task'' |
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292 | test_10_02_02_1_2.v:29: error: Could not find variable ``foo3'' in ``test.my_task'' |
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293 | test_10_02_02_1_2.v:30: error: Unable to bind wire/reg/memory `foo1' in `test.my_task' |
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294 | test_10_02_02_1_2.v:31: error: Unable to bind wire/reg/memory `foo2' in `test.my_task' |
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295 | test_10_02_02_1_2.v:32: error: Unable to bind wire/reg/memory `foo3' in `test.my_task' |
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296 | </pre> |
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297 | # test_10_03_00_1.v |
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298 | <pre> |
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299 | test_10_03_00_1.v:25: syntax error |
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300 | test_10_03_00_1.v:26: error: invalid module item. |
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301 | test_10_03_00_1.v:27: syntax error |
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302 | test_10_03_00_1.v:27: error: invalid module item. |
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303 | test_10_03_00_1.v:28: syntax error |
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304 | test_10_03_00_1.v:28: error: Invalid module instantiation |
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305 | </pre> |
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306 | # test_10_03_00_2.v |
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307 | <pre> |
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308 | test_10_03_00_2.v:27: syntax error |
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309 | test_10_03_00_2.v:28: error: invalid module item. |
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310 | test_10_03_00_2.v:30: syntax error |
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311 | test_10_03_00_2.v:30: error: invalid module item. |
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312 | test_10_03_00_2.v:31: syntax error |
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313 | </pre> |
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314 | # test_10_03_00_3.v |
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315 | <pre> |
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316 | test_10_03_00_3.v:30: error: Unable to bind wire/reg/memory `a' in `test.proc_a' |
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317 | test_10_03_00_3.v:30: error: Unable to elaborate condition expression. |
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318 | </pre> |
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319 | # test_10_03_00_4.v |
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320 | <pre> |
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321 | test_10_03_00_4.v:34: syntax error |
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322 | test_10_03_00_4.v:35: error: invalid module item. |
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323 | test_10_03_00_4.v:35: syntax error |
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324 | test_10_03_00_4.v:35: error: Invalid module instantiation |
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325 | test_10_03_00_4.v:35: error: Invalid module instantiation |
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326 | test_10_03_00_4.v:39: error: Invalid module instantiation |
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327 | test_10_03_00_4.v:40: error: Invalid module instantiation |
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328 | test_10_03_00_4.v:43: error: invalid module item. |
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329 | test_10_03_00_4.v:44: syntax error |
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330 | test_10_03_00_4.v:44: error: Invalid module instantiation |
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331 | test_10_03_00_4.v:45: error: Invalid module instantiation |
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332 | </pre> |
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333 | # test_10_03_00_5.v |
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334 | <pre> |
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335 | test_10_03_00_5.v:28: syntax error |
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336 | </pre> |
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337 | # test_10_04_05_1.v |
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338 | <pre> |
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339 | test_10_04_05_1.v:27: sorry: constant user functions are not currently supported: clogb2(). |
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340 | </pre> |
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341 | # test_11_05_00_1.v |
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342 | <pre> |
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343 | test_11_05_00_1.v:29: error: reg p; cannot be driven by primitives or continuous assignment. |
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344 | </pre> |
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345 | # test_12_02_00_1.v |
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346 | <pre> |
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347 | test_12_02_00_1.v:54: syntax error |
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348 | </pre> |
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349 | # test_12_02_00_2.v |
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350 | <pre> |
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351 | test_12_02_00_2.v:28: error: Port a (1) of module foo is not declared within module. |
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352 | test_12_02_00_2.v:28: error: Port b (2) of module foo is not declared within module. |
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353 | test_12_02_00_2.v:28: error: no wire/reg a in module bar.f1. |
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354 | test_12_02_00_2.v:28: error: no wire/reg b in module bar.f1. |
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355 | </pre> |
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356 | # test_12_02_01_1.v |
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357 | <pre> |
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358 | test_12_02_01_1.v:29: syntax error |
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359 | </pre> |
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360 | # test_12_02_02_1_2.v |
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361 | <pre> |
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362 | test_12_02_02_1_2.v:28: error: Port addr (1) of module my_mem is not declared within module. |
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363 | test_12_02_02_1_2.v:28: error: Port data (2) of module my_mem is not declared within module. |
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364 | test_12_02_02_1_2.v:28: error: no wire/reg addr in module top.m. |
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365 | test_12_02_02_1_2.v:28: error: no wire/reg data in module top.m. |
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366 | </pre> |
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367 | # test_12_03_03_2.v |
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368 | <pre> |
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369 | test_12_03_03_2.v:46: syntax error |
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370 | test_12_03_03_2.v:46: error: missing endmodule or attempt to nest modules. |
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371 | test_12_03_03_2.v:40: error: original module (complex_ports) defined here. |
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372 | test_12_03_03_2.v:52: syntax error |
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373 | test_12_03_03_2.v:52: error: missing endmodule or attempt to nest modules. |
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374 | test_12_03_03_2.v:40: error: original module (complex_ports) defined here. |
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375 | test_12_03_03_2.v:56: syntax error |
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376 | test_12_03_03_2.v:56: error: missing endmodule or attempt to nest modules. |
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377 | test_12_03_03_2.v:40: error: original module (complex_ports) defined here. |
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378 | test_12_03_03_2.v:61: syntax error |
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379 | test_12_03_03_2.v:61: error: missing endmodule or attempt to nest modules. |
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380 | test_12_03_03_2.v:40: error: original module (complex_ports) defined here. |
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381 | test_12_03_03_2.v:65: syntax error |
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382 | test_12_03_03_2.v:65: error: missing endmodule or attempt to nest modules. |
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383 | test_12_03_03_2.v:40: error: original module (complex_ports) defined here. |
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384 | test_12_03_03_2.v:66: error: port a already has a port declaration. |
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385 | test_12_03_03_2.v:62: error: Port ``a'' has already been declared a port. |
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386 | </pre> |
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387 | # test_12_03_06_1.v |
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388 | <pre> |
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389 | test_12_03_06_1.v:34: error: port ``Out'' is not a port of instance1. |
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390 | test_12_03_06_1.v:34: error: port ``In1'' is not a port of instance1. |
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391 | test_12_03_06_1.v:34: error: port ``In2'' is not a port of instance1. |
||
392 | </pre> |
||
393 | # test_12_03_07_1.v |
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394 | <pre> |
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395 | test_12_03_07_1.v:29: error: Scalar port ``net_r'' has a vectored net declaration [64:1]. |
||
396 | test_12_03_07_1.v:34: error: Scalar port ``net_r'' has a vectored net declaration [64:1]. |
||
397 | test_12_03_07_1.v:36: error: Unable to bind wire/reg/memory `net_r' in `receiver' |
||
398 | ivl: netmisc.cc:467: void eval_expr(NetExpr*&, int): Assertion `expr' failed. |
||
399 | </pre> |
||
400 | # test_12_04_01_1.v |
||
401 | <pre> |
||
402 | test_12_04_01_1.v:49: syntax error |
||
403 | </pre> |
||
404 | # test_12_04_01_2.v |
||
405 | <pre> |
||
406 | test_12_04_01_2.v:39: syntax error |
||
407 | </pre> |
||
408 | # test_12_04_01_5.v |
||
409 | <pre> |
||
410 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
411 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
412 | test_12_04_01_5.v:33: error: Unknown module type: M2 |
||
413 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
414 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
415 | test_12_04_01_5.v:33: error: Unknown module type: M2 |
||
416 | test_12_04_01_5.v:31: error: Unknown module type: M1 |
||
417 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
418 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
419 | test_12_04_01_5.v:33: error: Unknown module type: M2 |
||
420 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
421 | test_12_04_01_5.v:35: error: Unknown module type: M3 |
||
422 | test_12_04_01_5.v:33: error: Unknown module type: M2 |
||
423 | test_12_04_01_5.v:40: error: Unknown module type: M4 |
||
424 | test_12_04_01_5.v:40: error: Unknown module type: M4 |
||
425 | test_12_04_01_5.v:31: error: Unknown module type: M1 |
||
426 | *** These modules were missing: |
||
427 | M1 referenced 2 times. |
||
428 | M2 referenced 4 times. |
||
429 | M3 referenced 8 times. |
||
430 | M4 referenced 2 times. |
||
431 | *** |
||
432 | </pre> |
||
433 | # test_12_04_02_1.v |
||
434 | <pre> |
||
435 | test_12_04_02_1.v:46: syntax error |
||
436 | test_12_04_02_1.v:46: error: invalid module item. |
||
437 | </pre> |
||
438 | # test_12_04_02_2.v |
||
439 | <pre> |
||
440 | test_12_04_02_2.v:44: error: Wrong number of ports. Expecting 0, got 3. |
||
441 | </pre> |
||
442 | # test_12_04_02_3.v |
||
443 | <pre> |
||
444 | test_12_04_02_3.v:26: error: Cannot evaluate genvar case expression: WIDTH |
||
445 | </pre> |
||
446 | # test_12_04_02_4.v |
||
447 | <pre> |
||
448 | test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0 |
||
449 | test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0 |
||
450 | test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0 |
||
451 | test_12_04_02_4.v:38: error: Unknown module type: sms_08b216t0 |
||
452 | *** These modules were missing: |
||
453 | sms_08b216t0 referenced 4 times. |
||
454 | *** |
||
455 | </pre> |
||
456 | |||
457 | # test_12_06_00_1.v |
||
458 | <pre> |
||
459 | test_12_06_00_1.v:34: error: Could not find variable ``b_c1.i'' in ``a._b1'' |
||
460 | test_12_06_00_1.v:34: error: Could not find variable ``b_c1.i'' in ``d.d_b1'' |
||
461 | test_12_06_00_1.v:53: error: Could not find variable ``a.a_b1.i'' in ``d'' |
||
462 | test_12_06_00_1.v:55: error: Could not find variable ``a.a_b1.b_c1.i'' in ``d'' |
||
463 | test_12_06_00_1.v:56: error: Could not find variable ``d.d_b1.b_c1.i'' in ``d'' |
||
464 | test_12_06_00_1.v:57: error: Could not find variable ``a.a_b1.b_c2.i'' in ``d'' |
||
465 | 1 | Sergey Smolov | </pre> |