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Icarus Verilog Bugs » History » Version 1

Sergey Smolov, 04/27/2018 02:50 PM

1 1 Sergey Smolov 
h1. Icarus Verilog Bugs
2 





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The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests"). 





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# test_03_08_01_1.v





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<pre>





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test_03_08_01_1.v:25: syntax error





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test_03_08_01_1.v:27: error: malformed statement





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test_03_08_01_1.v:28: syntax error





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test_03_08_01_1.v:33: error: malformed statement





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test_03_08_01_1.v:34: syntax error





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test_03_08_01_1.v:39: error: malformed statement





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test_03_08_01_1.v:40: syntax error





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</pre>





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# test_03_08_01_7.v





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<pre>





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test_03_08_01_7.v:25: syntax error





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test_03_08_01_7.v:25: error: malformed statement





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</pre>





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# test_04_03_01_1.v





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<pre>





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test_04_03_01_1.v:24: sorry: trireg nets not supported.





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</pre>





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# test_04_03_02_1.v





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<pre>





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test_04_03_02_1.v:22: syntax error





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test_04_03_02_1.v:22: error: invalid module item.





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test_04_03_02_1.v:23: syntax error





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test_04_03_02_1.v:23: error: invalid module item.





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</pre>





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# test_04_04_01_1.v





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<pre>





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test_04_04_01_1.v:22: sorry: trireg nets not supported.





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test_04_04_01_1.v:23: sorry: trireg nets not supported.





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test_04_04_01_1.v:25: syntax error





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test_04_04_01_1.v:25: error: invalid module item.





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</pre>





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# test_05_02_01_4.v





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<pre>





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test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'





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test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'





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</pre>





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# test_05_03_00_1.v





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<pre>





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test_05_03_00_1.v:25: warning: choosing typ expression.





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</pre>





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# test_06_01_03_1.v





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<pre>





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test_06_01_03_1.v:24: sorry: net delays not supported.





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</pre>





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# Compile test_07_14_01_1.v





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<pre>





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test_07_14_01_1.v:25: warning: choosing typ expression.





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test_07_14_01_1.v:25: warning: choosing typ expression.





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test_07_14_01_1.v:25: warning: choosing typ expression.





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test_07_14_01_1.v:26: warning: choosing typ expression.





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test_07_14_01_1.v:26: warning: choosing typ expression.





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test_07_14_01_1.v:26: warning: choosing typ expression.





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</pre>





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# test_07_14_01_2.v





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<pre>





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test_07_14_01_2.v:26: warning: choosing typ expression.





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test_07_14_01_2.v:27: warning: choosing typ expression.





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</pre>





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# test_07_14_02_2_1.v





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<pre>





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test_07_14_02_2_1.v:25: sorry: trireg nets not supported.





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</pre>





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# test_07_14_02_2_2.v





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<pre>





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test_07_14_02_2_2.v:26: sorry: trireg nets not supported.





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</pre>





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# test_08_06_00_1.v





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<pre>





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test_08_06_00_1.v:46: syntax error





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test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.





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test_08_06_00_1.v:46: error: Invalid module instantiation





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</pre>





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# test_09_02_01_1.v





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<pre>





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test_09_02_01_1.v:31: error: part select rega[3:5] is reversed.





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</pre>





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# test_09_03_02_1.v





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<pre>





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test_09_03_02_1.v:32: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.





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test_09_03_02_1.v:37: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.





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test_09_03_02_1.v:38: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.





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</pre>





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# test_09_03_02_2.v





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<pre>





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test_09_03_02_2.v:33: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.





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</pre>