Getting Started » History » Revision 3
Revision 2 (Alexander Kamkin, 05/05/2014 02:52 PM) → Revision 3/11 (Alexander Kamkin, 05/06/2014 07:58 AM)
h1. Getting Started This is a step-by-step instruction for getting started with developing a VeriTrans backend and using it within the Verilog translator environment. The term _backend_ refers to a component that traverses an _abstract syntax tree_ (_AST_) of the Verilog description and processes it in some way (e.g., constructs the internal representation and/or converts the description into some other language). The document is illustrated by the example of @VerilogPrinter@ (see the package @ru.ispras.verilog.parser.sample@). h2. Developing a Backend Technically, a backend is a Java object that implements the @VerilogBackend@ interface (the method @start@). Here is an example: <pre><code class="java"> package ru.ispras.verilog.parser.sample; import ru.ispras.verilog.parser.VerilogBackend; import ru.ispras.verilog.parser.model.*; ... import ru.ispras.verilog.parser.walker.*; /** * This class illustrates development of a Verilog backend. back-end. * * @author <a href="mailto:kamkin@ispras.ru">Alexander Kamkin</a> */ public final class VerilogPrinter extends VerilogBackend { /** * Processes the abstract syntax tree (AST). {@inheritDoc} * * @param root the AST''s root. */ @Override public void start(final VerilogNode root) { ... } } </code></pre> To ease development of a backend, one can use @VerilogTreeWalker@, a VeriTrans class that implements AST traversal. The @VerilogTreeWalker@''s constructor takes two parameters: (1) a reference to the tree''s root and (2) a visitor to be applied to the tree nodes: <pre><code class="java"> import ru.ispras.verilog.parser.walker.*; public void start(final VerilogNode root) { VerilogTreeWalker walker = new VerilogTreeWalker(root, new VerilogNodePrinter()); walker.start(); walker.start(); } } </code></pre> h2. Registering a Backend