Overview
A simple utility aimed at generating C-Verilog synchronization components of a test environment:
| Component | Description |
| Testbench | a Verilog wrapper around the DUT that generates a clock signal, launches a test scenario, and does cycle-by-cycle synchronization w/ the test environment |
| VPI Media | a C API for accessing the DUT's inputs and outputs. It is used by higher-level mediators to transform stimuli to input signals and output signals to reactions |
| C Interface | C data structures representing the DUT's inputs and outputs together w/ functions for synchronizing the structures' state w/ the real signal values |
| VPI SysTF | Templates for system tasks/functions used by Testbench: a scenario launcher and a synchronizer being called at each clock cycle |
The utility is implemented as a back-end for Icarus Verilog, an open-source Verilog simulator.
The utility is used by C++TESK, an open-source tool for developing test environments in C++.
Members
Manager: Alexander Kamkin, Mikhail Chupilko
Developer: Alexander Kamkin, Mikhail Chupilko, Nikita Chertok, Sergey Smolov
Project Creator: Alexander Kamkin