A simple utility intended for generation of C-Verilog synchronization components of a test system:

  • TestBench (a Verilog wrapper around the target module that launches a test scenario and generates a periodical clock pulse);
  • VPI-Mediator (a C API for accessing the target module's inputs and outputs);
  • C-Interface (C data structures modelling the inputs and outputs as well as functions for synchronizing those structures with the real signals);
  • VPI-SysTF (VPI functions being called from TestBench: scenario launcher and clock pulse handler).

The tool is implemented as a back-end for the open-source Verilog simulator Icarus Verilog.

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Feature 0 2 2
Support 0 1 1
Task 10 18 28

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