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Guarded actions extraction method » History » Version 3

Sergey Smolov, 03/09/2013 07:03 PM

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h1. Guarded actions extraction method
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h2. Concept
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The prototype of guarded actions extraction method is implemented in Retrascope project. This algorithm is based on IG representation of VHDL models, so guards and actions are extracted from corresponding IG constructions. It is _IGSequentialAssignment_ classes for actions, and _IGSequentialIf_/_IGSequentialWait_ constructions (more concrete, the conditions from these constructions) for guards.
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The method prototype is implemented in _ru.ispras.retrascope.gaa.extraction.GAExtractor_ class. A small example of it''s possibilities you can see at _ru.ispras.retrascope.gaa.tests.GAAExtractorTest_ test. This test:
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1. Performs VHDL model into IG representation by using ZamiaCAD engine;
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2. Calls method _extractGuardedActions(ZamiaProject, IGModule)_ for actions and guards extraction;
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3. Prints the result into console as list of pairs "guard-action" (also it is possible to save the result of the extraction into extracted_gaa.txt file)
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h2. Informal method description
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The algorithm walks through IG graph recursively. If it takes _IGSequentialIf_ construction, it writes it''s condition into guard predicate. While analysis of this construction statements it is took into account are they executed when the guard is true (i.e. then-branch) or false (else-branch). Corresponding parts of the resulting guard predicate are stored with TRUE or FALSE labels. The directives themselves are also stored in accordance with guard predicates.
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Pairs "guard-action" are also extracted from assignment statements.
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h2. Implementation details
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The algorithm returns an object of _java.util.ArrayList_, which elements have type _Guarded Action_. This class keeps two main fields: _Guard_ field and _Action_ field. Both of them keeps code fragments in (if it is possible) constraint-based form.
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h2. Application area
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The algorithm can be applied both single module and multi-module VHDL design because of pecularities of ZamiaCAD (this engine performs multi=module VHDL design into single IG graph).