Clock extraction method


The prototype of clock extraction method is implemented in Retrascope project.
Clock is an input signal of module, that is not an array, and it's value is not used in assignments.

Implementation details

The method prototype is implemented in ru.ispras.retrascope.gaa.extraction.ClockExtractor class. It is possible to test it by running ru.ispras.retrascope.gaa.tests.ClockExtractorTest. This test:
1) Performs VHDL model into Zamia IG - inner representation, that is created by ZamiaCAD engine;
2) Calls extractClockListFromModule(ZamiaProject, IGModule) target method;
3) Prints result of the extraction as list of signal names.

Informal method description

Clock extraction algorithm has two main steps. First of all, it performs an analysis of all interface signals of module: both input and output. If current signal satisfies to the definition of clock (that is described above), then it is added to list of hypothetical clocks.
Secondly, algorithm walks through IG graph recursively, and if it finds in IGoperationObject (an object, that participates in assignments) some element from list of hypothetical clocks, than algorithm removes this element from list. Algorithm does not process conditions from "if"\"when" constructions.

Application area

The algorithm can be applied both single module and multi-module VHDL design because of pecularities of ZamiaCAD (this engine performs multi=module VHDL design into single IG graph).

Updated by Sergey Smolov almost 7 years ago · 1 revisions