The new release includes the following changes:
- Support for loops in VHDL/Verilog designs;
- Support for wait-expressions in VHDL/Verilog designs;
- Support for hierarchical (i.e. having sub-modules) VHDL/Verilog designs;
- Support for concurrent (non-blocking) statements in VHDL/Verilog designs;
- New command line scripts for Windows & Unix;
- New heuristic for initial EFSM state & reset signal detection;
- New fully-functional *.tar.gz distribution format;
- A number of bugs was fixed.
The tool can be downloaded from here: http://forge.ispras.ru/projects/retrascope/files
We are happy to announce the first build of the HDL Retrascope toolkit.
HDL Retrascope is a toolkit for Reverse Engineering and TRAnsformation of digital hardware designs described in such HDLs (hardware description languages) as Verilog и VHDL. The toolkit allows analyzing HDL descriptions, reconstructing the underlying models (extended finite state machines, EFSMs) and using the derived models for test generation, property checking and other tasks. HDL Retrascope is organized as an extendable framework with the ability to add new types of models as well as tools for their analysis and transformation. The primary application domain of the toolkit is functional verification of hardware at the unit level.
To reconstruct EFSM models and generate tests for them, Retrascope requires the SMT-solver be installed. See Installation Guide for more information.
In the 0.1.1 build the following features have been implemented:
- Support for VHDL/Verilog little-size designs (without iteration loops/functions/sub-modules);
- Support for control flow graph (CFG) construction;
- Support for CFG visualization in GraphML format;
- Support for interface signals extraction from CFG;
- Support for guarded actions decision diagram (GADD) construction;
- Support for GADD visualization in GraphML format;
- Support for extended finite state machine (EFSM) extraction;
- Support for EFSM visualization in GraphML format;
- Support for read/write conflicts extraction from EFSM;
- Support for conflicts saving into XML format;
- Support for test sequences generation for EFSM;
- Support for test sequences saving into VHDL testbenches/XML format.
The tool can be downloaded from here: http://forge.ispras.ru/projects/retrascope/files
You are welcome to report bugs and leave your feedback at the main project site: http://forge.ispras.ru/projects/retrascope
Merry Christmas and Happy New Year!
The HDL-to-EFSM extraction method used in HDL Retrascope will be presented at the All-Russia Science & Technology Conference
Problems of Advanced Micro- and Nanoelectronic Systems Development (MES) - the largest conference in the field of CAD microelectronics in Russia and CIS countries. The conference will take place on September 29 - October 3 in Zelenograd, Moscow.
The HDL Retrascope tool will be introduced at the University Booth and PhD Forum of the Design Automation Conference (DAC) - the premier conference for design and automation of electronic systems. The conference will take place on June 1-5 in San Francisco, CA, USA.
DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design. Read more...