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Found Errors » History » Version 3

Sergey Smolov, 08/09/2018 02:38 PM

1 1 Sergey Smolov
h1. Found Errors
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3 3 Sergey Smolov
1. 
4 1 Sergey Smolov
src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer1 -> RDealer1
5 2 Sergey Smolov
src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer2 -> RDealer2
6 3 Sergey Smolov
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<pre><code class="diff">
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--- a/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v
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+++ b/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v
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@@ -14,7 +14,7 @@ module Control(
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         SESel,
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         Reset,
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-        Clk ,
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+        Clk// ,
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               );
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    reg monitor_lw;
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    reg monitor_j;
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</code></pre>