Found Errors » History » Version 3
Sergey Smolov, 08/09/2018 02:38 PM
1 | 1 | Sergey Smolov | h1. Found Errors |
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2 | |||
3 | 3 | Sergey Smolov | 1. |
4 | 1 | Sergey Smolov | src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer1 -> RDealer1 |
5 | 2 | Sergey Smolov | src/main/verilog/texas97-benchmarks/Blackjack/dp.v: RDelaer2 -> RDealer2 |
6 | 3 | Sergey Smolov | |
7 | 2. |
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8 | <pre><code class="diff"> |
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9 | --- a/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v |
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10 | +++ b/src/main/verilog/texas97-benchmarks/DLX/PDLX/control.v |
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11 | @@ -14,7 +14,7 @@ module Control( |
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12 | SESel, |
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13 | |||
14 | Reset, |
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15 | - Clk , |
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16 | + Clk// , |
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17 | ); |
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18 | reg monitor_lw; |
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19 | reg monitor_j; |
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20 | </code></pre> |