MMU Description¶

_{By Alexander Kamkin and Taya Sergeeva}

UNDER CONSTRUCTION

• Table of contents
• MMU Description
  • Grammar
  • Address Description
    • Grammar
    • Address Width (width)
      • Grammar
    • Address Format (format)
      • Grammar
  • Examples
  • Buffer Description
    • Grammar
    • Buffer Associativity (ways)
      • Grammar
    • Buffer Length (sets)
      • Grammar
    • Buffer Line Format (format)
      • Grammar
    • Buffer Index Function (index)
      • Grammar
    • Buffer Match Predicate (match)
    • Buffer Data Replacement Policy (policy)
      • Grammar
    • Examples

A memory management unit (MMU) is known to be one of the most complex and error-prone components of a modern microprocessor. MicroTESK has a special subsystem, called MMU subsystem, intended for (1) specifying memory devices and (2) deriving testing knowledge from such specifications. The subsystem provides unified facilities for describing memory buffers (like L1 and L2 caches, translation look-aside buffers (TLBs), etc.) as well as a means for connecting several buffers into a memory hierarchy.

Grammar¶

startRule 
    : bufferOrAddress*
    ;

bufferOrAddress
    : address
    | buffer
    ;

Address Description¶

A buffer is accessed by an address, which is typically a bit vector of a fixed length (width). Different buffers are allowed to have a common address space (e.g., L1 and L2 are usually both addressed by physical addresses). However, in general case, each buffer has its own domain.

An address space is described using a keyword address. The description can specify two parameters: width (obligatory) and format (optional).

Grammar¶

address
    : ''address'' ID ''{''
        (addressParameter '';'')*
      ''}''
    ;

addressParameter
    : width
    | format
    ;

Address Width (width)¶

The width parameter specifies the address width. The parameter is obligatory.

Grammar¶

width
    : ''width'' ''='' expr
    ;

Address Format (format)¶

The format parameter specifies the address format (a number of named fields). The parameter is optional. By default, the address is unstructured.

Grammar¶

format
    : ''format'' ''='' ''(''
        field ('','' field)*
      '')''
    ;

field
    : ID '':'' expr (''='' expr)?
    ;

Examples¶

// The singleton.
address Void {
  width = 0;
}

// An unstructured 64-bit virtual addresses.
address VA {
  width = 64;
}

// A stuctured 40-bit physical addresses.
address PA {
  width = 40;
  format = (tag:24, l1Index:7, dwPosition:2, bytePosition:3);
}

The code above defines three address spaces: (1) a singleton Void; (2) a space VA consisting of 64-bit addresses (virtual addresses) and (3) a space PA consisting of 40-bit addresses (physical addresses), each being divided into for fields: tag (24 bits), l1Index (7 bits), dwPosition (2 bits) and bytePosition (3 bits).

Buffer Description¶

A buffer is described using a keyword buffer. The description specifies a set of parameters, including ways, sets, format, index, match and policy. All of the parameters except index (if sets = 1) and policy are obligatory.

Grammar¶

buffer
    : ''buffer'' ID ''{''
        (bufferParameter '';'')*
      ''}''
    ;

bufferParameter
    : ways
    | sets
    | format
    | index
    | match
    | policy
    ;

Buffer Associativity (ways)¶

The ways parameter specifies the buffer associativity (the number of lines in a set). The parameter is obligatory.

Grammar¶

ways
    : ''ways'' ''='' expr
    ;

Buffer Length (sets)¶

The sets parameter specifies the buffer length (the number of lines a cache). The parameter is obligatory.

Grammar¶

sets
    : ''sets'' ''='' expr
    ;

Buffer Line Format (format)¶

line is an optional description of line''s fields;
  it designates each line of the cache; 
  line includes its own parameters in the braces: tag and data, each of them has an appropriate width of the fields kept in bytes;

Grammar¶

Buffer Index Function (index)¶

index is the function for index calculation;
   returns the initial and the final points of the field kept in bytes; they are marked in a three-cornered brackets, after addr; in our case index has 2 bits;
  index depends on an address, which is ''physical'' (PA) in our case; the type of an address is set in the braces after index;

Grammar¶

Buffer Match Predicate (match)¶

match is a predicate checking whether the line and the address match each other or not;
  it returns ''true'' or ''false'' depending on if the data required is in the given line or not; 
  it returns ''true'' if there is a ''hit'' in the line, and returns ''false'' otherwise; if the set contains a line with the tag equal to the 30 upper bits of the physical address, this is a ''hit''; if the set does not contain the line, this is a ''miss'' situation;
  match description contains the the initial and the final points of the address field in the triangle brackets after addr; 
  as index in the round braces match also has the type of the address used; ''PA'' in our case;

Buffer Data Replacement Policy (policy)¶

policy is the strategy of data displacement; 
  sets a policy which will be applied to our buffer, ''lru'' (Least Recently Used) in our example; 
  policy also can be ''plru'' (Pseudo LRU) and ''fifo'' (First Input First Out).

Grammar¶

Examples¶

Let as consider a simple buffer which has only 2 attributes, such as the associativity, associativity, i.e. the set''s size, and the number of sets in the buffer, sets.

buffer TLB { 
  ways = 8;
  sets = 64;
} 

The example above describes translation lookaside buffer (TLB), which has an associativity being equal to 8, (i.e. the number of lines in one set in this TLB buffer is equal to 8), and has the number of lines being equal to 64.

Each line of the buffer can be described optionally by tag and data parameters.
For example,

line = (tag:22, data:1024);

describes lines of the cache, each of them containing a 22-bit tag and 1024-bit data.

In a MMU buffer also can have the index computing function. When accessing data, the cache determines a set by calculating a x-bit index. For example,

index(addr:PA) = addr<14..13>;

The cache calculates a 2-bit index. index returns the initial and the final points of the field kept in bytes.

Each device stores some data which can be accessed (read from or written into) by their address. If a device contains a line with a given address, this situation is called a ''hit''; the opposite situation referes to as a ''miss''. If a ''miss'' occurs, the device usually displaces one of the set''s line with the line associated with the address given. The predicate which determines if there is a ''miss'' or ''hit'' situation is called match. There is the example below:

line = (tag:22, data:1024);
match(addr:VA) = line.tag == addr<14..1>;

If the set contains a line with the tag equal to the 22 upper bits of the physical address, this is a ''hit''. match returns ''true'' if there is a ''hit'' in the line, and returns ''false'' otherwise.

The strategy which will be used for the lines displacement is specified by policy.

policy = LRU;

Example above sets the strategy of data replacement to be Last Recently Used policy, i.e. if the ''miss'' occured, the cache displaces the least-recently-used line of the set.

There is the example below, describing a real ''lower-level'' cache L1:

buffer L1 
{
    associativity = 4;
    sets = 128;
    line = (tag:30, data:256);
    index(addr:PA) = addr<9..8>;
    match(addr:PA) = line.tag == addr<39..10>;
    policy = lru;
}

Description of each constructor in the buffer example is below: