Project

General

Profile

MMU description » History » Version 72

Alexander Kamkin, 12/01/2014 02:27 PM

1 24 Alexander Kamkin
h1. MMU Description
2 1 Taya Sergeeva
3 66 Alexander Kamkin
_~By Alexander Kamkin and Taya Sergeeva~_
4 62 Alexander Kamkin
5 65 Alexander Kamkin
*UNDER CONSTRUCTION*
6
7 63 Alexander Kamkin
{{toc}}
8
9 35 Alexander Kamkin
A _memory management unit_ (_MMU_) is known to be one of the most complex and error-prone components of a modern microprocessor. MicroTESK has a special subsystem, called _MMU subsystem_, intended for (1) specifying memory devices and (2) deriving testing knowledge from such specifications. The subsystem provides unified facilities for describing memory buffers (like _L1_ and _L2 caches_, _translation look-aside buffers_ (_TLBs_), etc.) as well as a means for connecting several buffers into a memory hierarchy.
10 1 Taya Sergeeva
11 72 Alexander Kamkin
h2. Grammar
12 66 Alexander Kamkin
13
<pre>
14
startRule 
15
    : bufferOrAddress*
16
    ;
17
18
bufferOrAddress
19
    : address
20
    | buffer
21
    ;
22
</pre>
23
24 1 Taya Sergeeva
h2. Address Description
25 56 Taya Sergeeva
26 1 Taya Sergeeva
A buffer is accessed by an _address_, which is typically a _bit vector_ of a fixed length (width). Different buffers are allowed to have a common address space (e.g., L1 and L2 are usually both addressed by physical addresses). However, in general case, each buffer has its own domain.
27
28 68 Alexander Kamkin
An address space is described using a keyword *address*. The @width@ and @format@ optional parameters can be specified inside the address space definition.
29 1 Taya Sergeeva
30 69 Alexander Kamkin
h4. Grammar
31
32
<pre>
33
address
34
    : ''address'' ID ''{''
35
        (addressParameter '';'')*
36
      ''}''
37
    ;
38
39
addressParameter
40
    : width
41
    | format
42
    ;
43
</pre>
44
45 68 Alexander Kamkin
h3. Address Width Parameter
46 1 Taya Sergeeva
47 68 Alexander Kamkin
The @width@ parameter specifies the address width. The parameter is optional. The default value is @0@.
48 1 Taya Sergeeva
49 69 Alexander Kamkin
h4. Grammar
50
51
<pre>
52
width
53
    : ''width'' ''='' expr
54
    ;
55
</pre>
56
57 68 Alexander Kamkin
h3. Address Format Parameter
58
59
The @format@ parameter specifies the address format (a number of named fields). The parameter is optional. By default, the address is unstructured.
60 1 Taya Sergeeva
61 69 Alexander Kamkin
h4. Grammar
62
63
<pre>
64
format
65
    : ''format'' ''='' ''(''
66
        field ('','' field)*
67
      '')''
68
    ;
69
70
field
71
    : ID '':'' expr (''='' expr)?
72
    ;
73
</pre>
74
75 72 Alexander Kamkin
h2. Examples
76 69 Alexander Kamkin
77 68 Alexander Kamkin
<pre>
78 66 Alexander Kamkin
// The singleton.
79
address Void {
80
  width = 0;
81
}
82
</pre>
83
84
<pre>
85
// An unstructured 64-bit virtual addresses.
86
address VA {
87
  width = 64;
88
}
89
</pre>
90
91
<pre>
92
// A stuctured 40-bit physical addresses.
93
address PA {
94
  width = 40;
95
  format = (tag:24, l1Index:7, dwPosition:2, bytePosition:3);
96
}
97
</pre>
98
99
</pre>
100
101
The code above defines three address spaces: (1) a singleton @Void@; (2) a space @VA@ consisting of 64-bit addresses (_virtual addresses_) and (3) a space @PA@ consisting of 40-bit addresses (_physical addresses_), each being divided into for fields: @tag@ (24 bits), @l1Index@ (7 bits), @dwPosition@ (2 bits) and @bytePosition@ (3 bits).
102
103
h3. Address Description Grammar
104
105 10 Alexander Kamkin
106 2 Taya Sergeeva
h2. Buffer Description
107 1 Taya Sergeeva
108 57 Taya Sergeeva
Buffer is described by the construct *buffer*. Buffer can have different parameters, such as an associativity, a number of lines, the tag computing function, the index computing function, and the structure of data unit displacement, the controlling bits, the strategies of data changing when ''miss'' occurs, and so on. 
109 1 Taya Sergeeva
110 64 Taya Sergeeva
Let as consider a simple buffer which has only 2 attributes, such as the associativity, *associativity*, i.e. the set''s size, and the number of sets in the buffer, *sets*. 
111 57 Taya Sergeeva
112 56 Taya Sergeeva
<pre>
113
buffer TLB 
114
{ 
115 64 Taya Sergeeva
  associativity=8;
116
  sets=64;
117 56 Taya Sergeeva
} 
118 1 Taya Sergeeva
</pre>
119
120 57 Taya Sergeeva
The example above describes translation lookaside buffer (_TLB_), which has an associativity being equal to 8, (i.e. the number of lines in one set in this TLB buffer is equal to 8), and has the number of lines being equal to 64.   
121 56 Taya Sergeeva
122 57 Taya Sergeeva
Each *line* of the buffer can be described optionally by _tag_ and _data_ parameters. 
123 56 Taya Sergeeva
For example, 
124
125 1 Taya Sergeeva
<pre>
126 56 Taya Sergeeva
line = (tag:22, data:1024);
127 1 Taya Sergeeva
</pre>
128 56 Taya Sergeeva
129 1 Taya Sergeeva
describes lines of the cache, each of them containing a 22-bit tag and 1024-bit data.
130 56 Taya Sergeeva
131 57 Taya Sergeeva
In a MMU buffer also can have the *index* computing function. When accessing data, the cache determines a set by calculating a x-bit index. For example,
132 56 Taya Sergeeva
133 1 Taya Sergeeva
<pre>
134 57 Taya Sergeeva
index(addr:PA) = addr<14..13>;
135 1 Taya Sergeeva
</pre>
136
137 57 Taya Sergeeva
The cache calculates a 2-bit index. _index_ returns the initial and the final points of the field kept in bytes.
138 1 Taya Sergeeva
139 57 Taya Sergeeva
Each device stores some data which can be accessed (read from or written into) by their address. If a device contains a line with a given address, this situation is called a ''hit''; the opposite situation referes to as a ''miss''. If a ''miss'' occurs, the device usually displaces one of the set''s line with the line associated with the address given. The predicate which determines if there is a ''miss'' or ''hit'' situation is called *match*. There is the example below:
140
141 56 Taya Sergeeva
<pre>
142 57 Taya Sergeeva
line = (tag:22, data:1024);
143
match(addr:VA) = line.tag == addr<14..1>;
144 56 Taya Sergeeva
</pre>
145
146 57 Taya Sergeeva
If the set contains a line with the tag equal to the 22 upper bits of the physical address, this is a ''hit''. _match_ returns ''true'' if there is a ''hit'' in the line, and returns ''false'' otherwise.
147 56 Taya Sergeeva
148 57 Taya Sergeeva
The strategy which will be used for the lines displacement is specified by *policy*. 
149 56 Taya Sergeeva
150 57 Taya Sergeeva
<pre>
151
policy = LRU;
152
</pre>
153 56 Taya Sergeeva
154 57 Taya Sergeeva
Example above sets the strategy of data replacement to be _Last_ _Recently_ _Used_ policy, i.e. if the ''miss'' occured, the cache displaces the least-recently-used line of the set.
155 56 Taya Sergeeva
156 57 Taya Sergeeva
There is the example below, describing a real ''lower-level'' cache L1: 
157 2 Taya Sergeeva
158 53 Taya Sergeeva
<pre>
159
buffer L1 
160
{
161 64 Taya Sergeeva
	associativity = 4;
162
	sets = 128;
163 53 Taya Sergeeva
	line = (tag:30, data:256);
164 10 Alexander Kamkin
	index(addr:PA) = addr<9..8>;
165 1 Taya Sergeeva
	match(addr:PA) = line.tag == addr<39..10>;
166
	policy = lru;
167
}
168
</pre>
169 19 Taya Sergeeva
170
_Description of each constructor_ in the buffer example is below:
171 49 Taya Sergeeva
172 21 Taya Sergeeva
h3. buffer
173 55 Taya Sergeeva
174 21 Taya Sergeeva
<pre>
175 1 Taya Sergeeva
  has a name, ''L1'' in our example; it can have names ''L2'' and ''TLB'' also;
176 64 Taya Sergeeva
  _buffer_ can be described by different parameters, such _associativity_, _sets_, _index_, _match_, _policy_, and so on, which number is infixed;
177 16 Taya Sergeeva
</pre>
178 15 Taya Sergeeva
179 64 Taya Sergeeva
h3.  associativity 
180 15 Taya Sergeeva
181 1 Taya Sergeeva
<pre>
182 64 Taya Sergeeva
  _associativity_ is an associativity of a buffer; it returns the number of lines in a one set;
183 17 Taya Sergeeva
</pre>
184 15 Taya Sergeeva
185 64 Taya Sergeeva
h3.  sets
186 15 Taya Sergeeva
187 13 Taya Sergeeva
<pre>
188 64 Taya Sergeeva
  _sets_ is the number of sets in a given buffer;
189 1 Taya Sergeeva
</pre>
190 17 Taya Sergeeva
191 54 Taya Sergeeva
h3.  line
192
193 1 Taya Sergeeva
<pre>
194 52 Taya Sergeeva
  _line_ is an optional description of line''s fields;
195 54 Taya Sergeeva
  it designates each line of the cache; 
196 14 Taya Sergeeva
  _line_ includes its own parameters in the braces: _tag_ and _data_, each of them has an appropriate width of the fields kept in bytes;
197 1 Taya Sergeeva
  in our example _line_ has only two parameters, but in general case it can include more;
198
  it contains a 30-bit tag and a 256-bit data;
199 49 Taya Sergeeva
</pre>
200 17 Taya Sergeeva
201 54 Taya Sergeeva
h3.  index
202
203 1 Taya Sergeeva
<pre>
204
   _index_ is the function for index calculation;
205
   returns the initial and the final points of the field kept in bytes; they are marked in a three-cornered brackets, after _addr_; in our case index has 2 bits;
206
  _index_ depends on an _address_, which is ''physical'' (PA) in our case; the type of an address is set in the braces after _index_; 
207 49 Taya Sergeeva
</pre>
208 17 Taya Sergeeva
209 54 Taya Sergeeva
h3.  match 
210
211
<pre>
212 1 Taya Sergeeva
  _match_ is a predicate checking whether the line and the address match each other or not;
213
  it returns ''true'' or ''false'' depending on if the data required is in the given line or not; 
214 52 Taya Sergeeva
  it returns ''true'' if there is a ''hit'' in the line, and returns ''false'' otherwise; if the set contains a line with the tag equal to the 30 upper bits of the physical address, this is a ''hit''; if the set does not contain the line, this is a ''miss'' situation;
215 1 Taya Sergeeva
  _match_ description contains the the initial and the final points of the address field in the triangle brackets after _addr_; 
216
  as _index_ in the round braces _match_ also has the type of the address used; ''PA'' in our case;
217
</pre>
218 49 Taya Sergeeva
219 1 Taya Sergeeva
h3.  policy
220 54 Taya Sergeeva
221 56 Taya Sergeeva
<pre>
222 52 Taya Sergeeva
  _policy_ is the strategy of data displacement; 
223 1 Taya Sergeeva
  sets a policy which will be applied to our buffer, ''lru'' (Least Recently Used) in our example; 
224 25 Alexander Kamkin
  policy also can be ''plru'' (Pseudo LRU) and ''fifo'' (First Input First Out).
225
</pre>
226
227
h2. Code Structure
228
229
The MMU grammar is in ru.ispras.microtesk.translator.mmu.grammar folder. It contains Lexer, Parser and TreeWalker files. These files can be compiled by build.xml file (microtesk++/build.xml). The files generated (MMULexer.java, MMUParser.java, MMUTreeWalker.java) are in microtesk++.gen.ru.ispras.microtesk.translator.mmu.grammar folder. 
230
231
The folders ru.ispras.microtesk.translator.mmu.ir.* contain the inner representation of the MMU hierarchy of one buffer.  
232 1 Taya Sergeeva
233
MMU translator is in the ru.ispras.microtesk.translator.mmu.translator folder. 
234 26 Alexander Kamkin
235
Files in ru.ispras.microtesk.model.api.mmu folder contain different policies of cache. Folder ru.ispras.microtesk.model.api.mmu.buffer contains the model of MMU - the files which describe Buffer, Set, Line, Address expressions.  
236 1 Taya Sergeeva
237
After grammar files being generated the file ''BufferExample'' can be loaded to the translator.