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MMU description » History » Version 126

Andrei Tatarnikov, 01/29/2015 04:18 PM

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h1. MMU Description
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_~By Alexander Kamkin and Taya Sergeeva~_
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{{toc}}
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A _memory management unit_ (_MMU_) is known to be one of the most complex and error-prone components of a modern microprocessor. MicroTESK has a special subsystem, called _MMU subsystem_, intended for (1) specifying memory devices and (2) deriving testing knowledge from such specifications. The subsystem provides unified facilities for describing memory buffers (like _L1_ and _L2 caches_, _translation look-aside buffers_ (_TLBs_), etc.) as well as a means for connecting several buffers into a memory hierarchy.
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h2. Grammar
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<pre>
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startRule
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    : declaration* EOF!
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    ;
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declaration
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    : address
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    | segment
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    | buffer
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    | mmu
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    ;
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</pre>
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The expression syntax is derived from nML/Sim-nML (see [[Sim-nML Language Reference]]).
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h2. Address Description (address)
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A buffer is accessed by an _address_, which is typically a _bit vector_ of a fixed length (width). Different buffers are allowed to have a common address space (e.g., L1 and L2 are usually both addressed by physical addresses). However, in general case, each buffer has its own domain.
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An address space is described using a keyword @address@. The description includes the address type _identifier_ and the address _width_. The latter is specified in brackets. Its value should be non-negative (zero-length addresses are permitted).
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h3. Grammar
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<pre>
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address
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    : ''address'' addressTypeID ''('' expr '')''
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    ;
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</pre>
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h3. Examples
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<pre>// A 64-bit virtual address (VA).
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address VA(64)</pre>
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<pre>// A 36-bit physical address (PA).
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address PA(36)</pre>
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h2. Address Space Segment Description (segment)
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An address space segment is specified using the @segment@ keyword. A segment is associated with a specific address type. It is possible to specify any number (&ge; 0) of segments (with different names) for one address type. Each segment is characterized by its _identifier_ and _address range_. Different segments should have different names, but address ranges are allowed to overlap, and moreover, to be the same.
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h3. Grammar
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<pre>
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segment
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    : ''segment'' segmentID ''('' argumentID '':'' addressTypeID '')''
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        ''range'' ''='' ''('' expr '','' expr '')''
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    ;
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</pre>
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h3. Examples
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<pre>
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segment USEG (va: VA)
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  range = (0x0000000000000000, 0x000000007fffffff)
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</pre>
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h2. Buffer Description (buffer)
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A buffer is described using a keyword @buffer@. The description specifies a set of parameters, including @ways@, @sets@, @entry@, @index@, @match@ and @policy@. All of the parameters except @index@ (if @sets = 1@) and @policy@ are obligatory.
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h3. Grammar
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<pre>
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buffer
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    : ''buffer'' bufferTypeID ''('' addressArgID '':'' addressTypeID '')''
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        (bufferParameter)*
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    ;
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bufferParameter
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    : ways
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    | sets
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    | entry
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    | index
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    | match
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    | policy
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    ;
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</pre>
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h3. Buffer Associativity (ways)
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The @ways@ parameter specifies the buffer _associativity_ (the number of lines in a set). The parameter is obligatory; its value should be positive.
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h4. Grammar
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<pre>
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ways
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    : ''ways'' ''='' expr
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    ;
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</pre>
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h3. Buffer Length (sets)
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The @sets@ parameter specifies the buffer _length_ (the number of sets a cache). The parameter is obligatory; its value should be positive.
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h4. Grammar
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<pre>
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sets
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    : ''sets'' ''='' expr
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    ;
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</pre>
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h3. Buffer Line Format (entry)
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The @entry@ parameter specifies the buffer _line format_ (a number of named fields). A field has three attributes: a name, a width and, optionally, an initial value.
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h4. Grammar
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<pre>
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format
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    : ''entry'' ''='' ''('' field ('','' field)* '')''
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    ;
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field
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    : fieldID '':'' expr (''='' expr)?
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    ;
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</pre>
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h3. Buffer Index Function (index)
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The @index@ parameter specifies the _address-to-index function_, which maps an address into the set index. The function may be omitted if the number of sets is @1@.
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h4. Grammar
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<pre>
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index
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    : ''index'' ''='' expr
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    ;
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</pre>
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h3. Buffer Match Predicate (match)
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The @match@ parameter specifies the _address-line match predicate_, which checks if an address matches a line. The parameter is obligatory.
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h4. Grammar
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<pre>
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index
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    : ''match'' ''='' expr
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    ;
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</pre>
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h3. Buffer Data Replacement Policy (policy)
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The @policy@ parameters specifies the _data replacement_ (_eviction_) _policy_. The parameter is optional. The list of supported policies includes: @RANDOM@, @FIFO@, @PLRU@ and @LRU@.
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h4. Grammar
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<pre>
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policy
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    : ''policy'' ''='' policyID
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    ;
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</pre>
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h3. Examples
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<pre>
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// A 4-way set associative cache (L1) addressed by physical addresses (PA).
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buffer L1(addr: PA)
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  // The cache associativity.
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  ways = 4
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  // The number of sets.
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  sets = 128
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  // The line format.
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  entry = (
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    V    : 1 = 0, // The validity flag (by default, the line is invalid).
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    TAG  : 24,    // The tag (the <35..12> address bits).
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    DATA : 256    // The data (4 double words).
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  )
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  // The address-to-index function (example: using address fields).
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  index = addr.INDEX
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  // The address-line predicate (example: using address bits).
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  match = addr<35..12> == TAG
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  // The data replacement policy (example: using predefined policy LRU - Least Recently Used).
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  policy = LRU
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</pre>
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h2. MMU Description (mmu)
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Memory management unit logic is described using the @mmu@ keyword. The description includes two obligatory parameters @read@ and @write@ that describe the semantics of memory read and memory write actions respectively.
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h3. Grammar
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<pre>
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mmu
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    : ''mmu'' memoryTypeID ''('' addressArgID '':'' addressTypeID '')'' = dataArgID
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        (memoryParameter)*
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    ;
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mmuParameter
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    : ''read'' ''='' ''{'' sequence ''}''
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    | ''write'' ''='' ''{'' sequence ''}''
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    ;
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</pre>
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h3. Memory Read Action (read)
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The @read@ parameter specifies the _read action_, which is a sequence of statements describing how the read operation is to be performed (by means of data transfers between buffers). The parameter is obligatory.
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h4. Grammar
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<pre>
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read
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    : ''read'' ''='' ''{'' sequence ''}''
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    ;
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</pre>
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h3. Memory Write Action (write)
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The @write@ parameter specifies the _read action_, which is a sequence of statements describing how the write operation is to be performed (by means of data transfers between buffers). The parameter is obligatory.
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h4. Grammar
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<pre>
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write
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    : ''write'' ''='' ''{'' sequence ''}''
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    ;
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</pre>
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h3. Examples
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<pre>
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// A memory unit addressed by virtual addresses (VA).
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mmu Memory(addr: VA) = data
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  // The read action.
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  read = {
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    // Some statements.
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    ...
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  }
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  // The write action.
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  write = {
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    // Some statements.
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    ...
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  }
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</pre>