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Andrei Tatarnikov, 01/29/2015 02:13 PM

MMU Description

By Alexander Kamkin and Taya Sergeeva

A memory management unit (MMU) is known to be one of the most complex and error-prone components of a modern microprocessor. MicroTESK has a special subsystem, called MMU subsystem, intended for (1) specifying memory devices and (2) deriving testing knowledge from such specifications. The subsystem provides unified facilities for describing memory buffers (like L1 and L2 caches, translation look-aside buffers (TLBs), etc.) as well as a means for connecting several buffers into a memory hierarchy.


    : declaration* EOF!

    : address
    | segment
    | buffer
    | mmu

The expression syntax is derived from nML/Sim-nML (see Sim-nML Language Reference).

Address Description (address)

A buffer is accessed by an address, which is typically a bit vector of a fixed length (width). Different buffers are allowed to have a common address space (e.g., L1 and L2 are usually both addressed by physical addresses). However, in general case, each buffer has its own domain.

An address space is described using a keyword address. The description includes the address type identifier and the address width. The latter is specified in brackets. Its value should be non-negative (zero-length addresses are permitted).


    : ''address'' addressTypeID ''('' expr '')''


// A 64-bit virtual address (VA).
address VA(64)
// A 36-bit physical address (PA).
address PA(36)

Address Space Segment Description (segment)

An address space segment is specified using the segment keyword. A segment is associated with a specific address type. It is possible to specify any number (≥ 0) of segments (with different names) for one address type. Each segment is characterized by its identifier and address range. Different segments should have different names, but address ranges are allowed to overlap, and moreover, to be the same.


    : ''segment'' segmentID ''('' argumentID '':'' addressTypeID '')''
        ''range'' ''='' ''('' expr '','' expr '')''


segment USEG (va: VA)
  range = (0x0000000000000000, 0x000000007fffffff)


// The singleton.
address Void
  // The address width is zero (this is admissible for single-item buffers).
  width = 0
// An unstructured 64-bit virtual addresses (VA).
address VA
  // The address width.
  width = 64
// A stuctured 40-bit physical addresses (PA).
address PA
  // The address width.
  width = 40
  // The address format: (<39..36>, TAG=<35..12>, INDEX=<11..5>, LOCAL=<4..0>).
  format PA_L1 = (
    TAG   : 24, // The tag (the <35..12> address bits).
    INDEX : 7,  // The set index (the <11..5> address bits).
    LOCAL : 5,  // The byte position (the <0..4> address bits).

Buffer Description (buffer)

A buffer is described using a keyword buffer. The description specifies a set of parameters, including ways, sets, format, index, match and policy. All of the parameters except index (if sets = 1) and policy are obligatory.


    : ''buffer'' bufferTypeID ''('' addressTypeID addressArgID '')''

    : ways
    | sets
    | format
    | index
    | match
    | policy

Buffer Associativity (ways)

The ways parameter specifies the buffer associativity (the number of lines in a set). The parameter is obligatory; its value should be positive.


    : ''ways'' ''='' expr

Buffer Length (sets)

The sets parameter specifies the buffer length (the number of sets a cache). The parameter is obligatory; its value should be positive.


    : ''sets'' ''='' expr

Buffer Line Format (format)

The format parameter specifies the buffer line format (a number of named fields). Any number (≥ 0) of formats (with different names) can be specified for one buffer.

A field has three attributes: a name, a width and, optionally, an initial value.


    : ''format'' formatID ''='' ''('' field ('','' field)* '')''

    : fieldID '':'' expr (''='' expr)?

Buffer Index Function (index)

The index parameter specifies the address-to-index function, which maps an address into the set index. The function may be omitted if the number of sets is 1.


    : ''index'' ''='' expr

Buffer Match Predicate (match)

The match parameter specifies the address-line match predicate, which checks if an address matches a line. The parameter is obligatory.


    : ''match'' ''='' expr

Buffer Data Replacement Policy (policy)

The policy parameters specifies the data replacement (eviction) policy. The parameter is optional. The list of supported policies includes: RANDOM, FIFO, PLRU and LRU.


    : ''policy'' ''='' policyID


// A 4-way set associative cache (L1) addressed by physical addresses (PA).
buffer L1(PA addr)
  // The cache associativity.
  ways = 4
  // The number of sets.
  sets = 128
  // The line format.
  format LINE = (
    V    : 1 = 0, // The validity flag (by default, the line is invalid).
    TAG  : 24,    // The tag (the <35..12> address bits).
    DATA : 256    // The data (4 double words).
  // The address-to-index function (example: using address fields).
  index = addr.INDEX
  // The address-line predicate (example: using address bits).
  match = addr<35..12> == LINE.TAG
  // The data replacement policy (example: using predefined policy LRU - Least Recently Used).
  policy = LRU

Memory Description (memory)

A memory is described using a keyword memory. The description includes two obligatory parameters read and write.


    : ''memory'' memoryTypeID ''('' addressTypeID addressArgID '')''

    : read
    | write

Memory Read Action (read)

The read parameter specifies the read action, which is a sequence of statements describing how the read operation is to be performed (by means of data transfers between buffers). The parameter is obligatory.


    : ''read'' ''='' ''{'' sequence ''}''

Memory Write Action (write)

The write parameter specifies the read action, which is a sequence of statements describing how the write operation is to be performed (by means of data transfers between buffers). The parameter is obligatory.


    : ''write'' ''='' ''{'' sequence ''}''


// A memory unit addressed by virtual addresses (VA).
memory Memory(VA addr)
  // The read action.
  read = {
    // Some statements.
  // The write action.
  write = {
    // Some statements.

Updated by Andrei Tatarnikov over 5 years ago · 113 revisions