MicroTESK

h1. Constraint Solver

The constraint solver subsystem is aimed to provide the possibility to automatically generate test cases based on specified constraints. A constraint is represented by a set of limitations for input values. Solvers calculate values of input variables which will violate the limitations if there are any such values.

The subsystem uses an openly distributed SMT solver as an engine (in the current version, we use the Z3 solver by Microsoft Research). In SMT solvers, a special functional language is used to specify constraints. The constraint solver subsystem generates constructions in the SMT language and runs the engine to process them and produce the results (find values of unknown input variables).

h2. Constraints and Satisfiability Modulo Theories (SMT)

Constrains specified as an SMT model are represented by a set of assertions (formulas) that must be satisfied. An SMT solver checks the satisfiability of the model and suggests a solution (variable values) that would satisfy the model. In the example below, we specify a model that should help us create a test that will cause a MIPS processor to generate an exception. We want to find values of the rs and rt general purpose registers that will cause the ADD instruction to raise an integer overflow exception. It should be correct 32-bit signed integers that are not equal to each other. Here is an SMT script:

<pre>

(define-sort        Int_t () (_ BitVec 64))

(define-fun      INT_ZERO () Int_t (_ bv0 64))

(define-fun INT_BASE_SIZE () Int_t (_ bv32 64))

(define-fun INT_SIGN_MASK () Int_t (bvshl (bvnot INT_ZERO) INT_BASE_SIZE))

(define-fun IsValidPos ((x!1 Int_t)) Bool (ite (= (bvand x!1 INT_SIGN_MASK) INT_ZERO) true false))

(define-fun IsValidNeg ((x!1 Int_t)) Bool (ite (= (bvand x!1 INT_SIGN_MASK) INT_SIGN_MASK) true false))

(define-fun IsValidSignedInt ((x!1 Int_t)) Bool (ite (or (IsValidPos x!1) (IsValidNeg x!1)) true false))

(declare-const rs Int_t)

(declare-const rt Int_t)

; rt and rs must contain valid sign-extended 32-bit values (bits 63..31 equal)

(assert (IsValidSignedInt rs))

(assert (IsValidSignedInt rt))

; the condition for an overflow: the summation result is not a valid sign-extended 32-bit value

(assert (not (IsValidSignedInt (bvadd rs rt))))

; just in case: rs and rt are not equal (to make the results more interesting)

(assert (not (= rs rt)))

(check-sat)

(echo "Values that lead to an overflow:")

(get-value (rs rt))

</pre>

In an ideal case, each run of an SMT solver should return random values from the set of possible solutions. This should improve test coverage. Unfortunately, the current implementation is limited to a single solution that is constant for all run. This should be improved in the final version.   

h2. Tree Representation

In our system, we use context-independent syntax trees to represent constraints. These trees are then used to generate a representation that can be understood by a particular SMT solver. Generally, it is an SMT model that uses some limited set of solver features applicable to microprocessor verification. The syntax tree contains nodes of the following types:

# Constraint. This is the root node of the tree. It holds the list of unknown variables and the list of assertions (formulas) for these variables.

# Formula. Represents an assertion expression. Can be combined with other formulas to build a more complex expression (by applying logic OR, AND or NOT to it). The underlying expression must be a logic expression that can be solved to true or false.

# Operation. Represents an unary or binary operation with some unknown variable, some value or some expression as parameters.

# Variable.Represents an input variable. It can have an assigned value and, in such a case, will be treated as a value. Otherwise, it is an unknown variable. A variable includes a type as an attribute.

# Value. Specifies some known value of the specified type which can be accessed as an attribute.

Note: Operation, Variables and Value are designed to be treated polymorphically. This allows combining them to build complex expressions.

h2. Constraint Solver Java Library

The Constraint Solver subsystem is implemented in Java. The source code files are located in the "microtesk++/constraint-solver" folder. The Java classes are organized in the following packages:

# ru.ispras.microtesk.constraints - contains SMT model generation logic and solver implementations.

# ru.ispras.microtesk.constraints.syntax - contains classes implementing syntax tree nodes.

# ru.ispras.microtesk.constraints.syntax.types - contains code that specifies particular data types and operation types.

# ru.ispras.microtesk.constraints.tests - contains JUnit test cases.

h3. Core classes/interfaces

The syntax tree nodes are implemented in the following classes:

* Constraint. Parameterized by unknown Variables and Formulas.

* Formula. Parameterized by an Operation object.

* Operation. Implements SyntaxElement. Parameterized by operand objects implementing SyntaxElement and an operation type object implementing OperationType.

* Variable. Implements SyntaxElement.  

* Value. Implements SyntaxElement.

The SyntaxElement interface provides the ability to combine different kinds of elements into expressions.

Also, Operation objects are parameterized by objects   

The current implementation supports operations with the following data types:

# Bit vectors

# Booleans

Example ..... :

<pre>

class BitVectorIntegerOverflowTestCase implements SolverTestCase

{

	private static final int      BIT_VECTOR_LENGTH = 64;

	private static final DataType   BIT_VECTOR_TYPE = DataType.getBitVector(BIT_VECTOR_LENGTH);

	private static final Value             INT_ZERO = new Value(new BigInteger("0"), BIT_VECTOR_TYPE);

	private static final Value        INT_BASE_SIZE = new Value(new BigInteger("32"), BIT_VECTOR_TYPE);

	private static final Operation    INT_SIGN_MASK =

		new Operation(BitVectorOperation.BVSHL, new Operation(BitVectorOperation.BVNOT, INT_ZERO, null), INT_BASE_SIZE);

	private Operation IsValidPos(SyntaxElement arg)

	{

		return new Operation(LogicBooleanOperation.EQ, new Operation(BitVectorOperation.BVAND, arg, INT_SIGN_MASK), INT_ZERO);

	}

	private Operation IsValidNeg(SyntaxElement arg)

	{

		return new Operation(LogicBooleanOperation.EQ, new Operation(BitVectorOperation.BVAND, arg, INT_SIGN_MASK), INT_SIGN_MASK);

	}

	private Operation IsValidSignedInt(SyntaxElement arg)

	{

		return new Operation(LogicBooleanOperation.OR, IsValidPos(arg), IsValidNeg(arg));

	}

	public Constraint getConstraint()

	{

		Constraint constraint = new Constraint();

		Variable rs = new Variable("rs", BIT_VECTOR_TYPE, null);

		constraint.addVariable(rs);

		Variable rt = new Variable("rt", BIT_VECTOR_TYPE, null);

		constraint.addVariable(rt);

		constraint.addFormula(

			new Formula(

				IsValidSignedInt(rs)

			)

		);

		constraint.addFormula(

			new Formula(

				IsValidSignedInt(rt)

			)

		);

		constraint.addFormula(

			new Formula(

				new Operation(

					LogicBooleanOperation.NOT,

					IsValidSignedInt(new Operation(BitVectorOperation.BVADD, rs, rt)),

					null

				) 

			)

		);

		constraint.addFormula(

			new Formula(

				new Operation(LogicBooleanOperation.NOT, new Operation(LogicBooleanOperation.EQ, rs, rt), null)

			)

		);

		return constraint;

	}

	public Vector<Variable> getExpectedVariables()	

	{

		Vector<Variable> result = new Vector<Variable>();

		result.add(new Variable("rs", BIT_VECTOR_TYPE, new BigInteger("000000009b91b193", 16)));

		result.add(new Variable("rt", BIT_VECTOR_TYPE, new BigInteger("000000009b91b1b3", 16)));

		return result;	

	}

}

</pre>

h1. База данных ограничений

База данных ограничений строится автоматически в результате анализа формализованных спецификаций системы команд микропроцессора, выполненной на одном из ADL-языков (например, nML). Некоторые ситуации могут описываться вручную и добавляться в базу данных ограничений.