Instructions supported by MicroTESK for RISC-V¶

The table below shows the state of support for particular instructions in MicroTESK for RISC-V.

There are three stages of support marked with different colors:

Fully supported

Partially supported

Currently unsupported

To be supported in MicroTESK, instructions need to be described in formal specifications. The Specified column shows whether specific instructions were described in the specifications.

The instruction semantics described in specifications may be incomplete or invalid. Therefore, instruction specifications must be validated with tests (e.g. ones ported from https://github.com/riscv/riscv-tests). To perform validation, the tests are executed in an ISA simulator constructed on the basis of the specifications. The Validated column shows whether the specifications of specific instructions were validated with tests.

NOTE: Incomplete or invalid semantics of instruction in specifications does not that these instructions cannot be used in test programs. It just prevent using them in tests that require information on the current state of registers and memory (e.g. self-checking tests and constraint-based tests). In general, to generate random tests, only the syntax of instructions is required to be valid whereas the semantics may be incomplete.

Instruction Set	Instructions	Specified	Validated
RV32I (User)	LUI AUIPC JAL JALR BEQ BNE BLT BGE BLTU BGEU LB LH LW LBU LHU SB SH SW ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SRAI SLL SRL SRA ADD SUB SLT SLTU XOR OR AND	Yes (37/37)	Yes (37/37)
RV64I (User)	LWU LD SD ADDIW SLLIW SRLIW SRAIW ADDW SUBW SLLW SRLW SRAW	Yes (12/12)	Yes (12/12)
RV32I (System)	ECALL EBREAK FENCE FENCE.I MRET SRET URET WFI CSRRW CSRRS CSRRC CSRRWI CSRRSI CSRRCI	Yes (14/14)	No (0/14)
RV32M	MUL MULH MULHSU MULHU DIV DIVU REM REMU	Yes (8/8)	Yes (8/8)
RV64M	MULW DIVW DIVUW REMW REMUW	Yes (5/5)	Yes (5/5)
RV32A	LR.W SC.W AMOSWAP.W AMOADD.W AMOXOR.W AMOAND.W AMOOR.W AMOMIN.W AMOMAX.W AMOMINU.W AMOMAXU.W	Yes (11/11)	Yes (11/11)
RV64A	LR.D SC.D AMOSWAP.D AMOADD.D AMOXOR.D AMOAND.D AMOOR.D AMOMIN.D AMOMAX.D AMOMINU.D AMOMAXU.D	Yes (11/11)	Yes (11/11)
RV32F	FLW FSW FMADD.S FMSUB.S FNMSUB.S FNMADD.S FADD.S FSUB.S FMUL.S FDIV.S FSQRT.S FSGNJ.S FSGNJN.S FSGNJX.S FMIN.S FMAX.S FCVT.W.S FCVT.WU.S FMV.X.W (FMV.X.S) FEQ.S FLT.S FLE.S FCLASS.S FCVT.S.W FCVT.S.WU FMV.W.X (FMV.S.X)	Yes (26/26)	Partially (8/26) Including (8): FLW FSW FEQ_S FLE_S FLT_S FEQ_S FLE_S FLT_S
RV64F	FCVT.L.S FCVT.LU.S FCVT.S.L FCVT.S.LU	Yes (4/4)	Partially (0/4)
RV32D	FLD FSD FMADD.D FMSUB.D FNMSUB.D FNMADD.D FADD.D FSUB.D FMUL.D FDIV.D FSQRT.D FSGNJ.D FSGNJN.D FSGNJX.D FMIN.D FMAX.D FCVT.S.D FCVT.D.S FEQ.D FLT.D FLE.D FCLASS.D FCVT.W.D FCVT.WU.D FCVT.D.W FCVT.D.WU	Yes (26/26)	Partially (2/26) Including (2): FLD FSD
RV64D	FCVT.L.D FCVT.LU.D FMV.X.D FCVT.D.L FCVT.D.LU FMV.D.X	Yes (6/6)	No (0/6)
RVC	C.ADDI4SPN C.FLD C.LQ C.LW C.FLW C.LD C.FSD C.SQ C.SW C.FSW C.SD C.NOP C.ADDI C.JAL C.ADDIW C.LI C.ADDI16SP C.LUI C.SRLI C.SRLI64 C.SRAI C.SRAI64 C.ANDI C.SUB C.XOR C.OR C.AND C.SUBW C.ADDW C.J C.BEQZ C.BNEZ C.SLLI C.SLLI64 C.FLDSP C.LQSP C.LWSP C.FLWSP C.LDSP C.JR C.MV C.EBREAK C.JALR C.ADD C.FSDSP C.SQSP C.SWSP C.FSWSP C.SDSP	Yes (49/49)	Partially (36/49) Excluding (13): C.LQ C.FLW C.SQ C.FSW C.NOP C.SRLI64 C.SRAI64 C.SLLI64 C.LQSP C.FLWSP C.EBREAK C.SQSP C.FSWSP
RV64Q		No	No
RV32V	VADD VSUB VSL VSR VAND VOR VXOR VSEQ VSNE VSLT VSGE VCLIP VCVT VMPOP VMFIRST VEXTRACT VINSERT VMERGE VSELECT VSLIDE VDIV VREM VMUL VMULH VMIN VMAX VSGNJ VSGNJN VSGNJX VSQRT VCLASS VPOPC VADDI VSLI VSRI VANDI VORI VXORI VCLIPI VMADD VMSUB VNMADD VNMSUB	No	No
Total