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Plasma instruction set

сategory instructions amount
Arithmetic Logic Unit ADD rd,rs,rt
ADDI rt,rs,imm
ADDIU rt,rs,imm
ADDU rd,rs,rt
AND rd,rs,rt
ANDI rt,rs,imm
LUI rt,imm
NOR rd,rs,rt
OR rd,rs,rt
ORI rt,rs,imm
SLT rd,rs,rt
SLTI rt,rs,imm
SLTIU rt,rs,imm
SLTU rd,rs,rt
SUB rd,rs,rt
SUBU rd,rs,rt
XOR rd,rs,rt
XORI rt,rs,imm
17
Shifter SLL rd,rt,sa
SLLV rd,rt,rs
SRA rd,rt,sa
SRAV rd,rt,rs
SRL rd,rt,sa
SRLV rd,rt,rs
6
Multiply DIV rs,rt
DIVU rs,rt
MFHI rd
MFLO rd
MTHI rs
MTLO rs
MULT rs,rt
MULTU rs,rt
8
Branch BEQ rs,rt,offset
BGEZ rs,offset
BGEZAL rs,offset
BGTZ rs,offset
BLEZ rs,offset
BLTZ rs,offset
BLTZAL rs,offset
BNE rs,rt,offset
BREAK
J target
JAL target
JALR rs
JR rs
MFC0 rt,rd
MTC0 rt,rd
SYSCALL
16
Memory Access LB rt,offset(rs)
LBU rt,offset(rs)
LH rt,offset(rs)
LHU rt,offset(rs)
LW rt,offset(rs)
SB rt,offset(rs)
SH rt,offset(rs)
SW rt,offset(rs)
8
Total: 55
100%
50+%
0+%

References
http://opencores.org/project,plasma,opcodes

Updated by Alexander Protsenko almost 4 years ago · 1 revisions