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Instruction Set Architecture » History » Version 4

Alexander Protsenko, 03/16/2023 10:41 AM

1 1 Alexander Protsenko
h1. Instruction Set Architecture
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3 3 Alexander Protsenko
h2. Data processing - immediate
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h3. Arithmetic (immediate)
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### ADD (immediate). Add.
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Specification: add, add_32
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### SUB (immediate). Subtract.
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Specification: sub, sub_32
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### ADDS (immediate). Add and set flags.
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Specification: adds, adds_32
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### SUBS (immediate). Subtract and set flags.
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Specification: subs, subs_32
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### CMP (immediate). Compare.
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Specification: cmp, cmp_32
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### CMN (immediate). Compare negative.
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Specification: cmn, cmn_32
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h3. Logical (immediate)
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### AND (immediate). Bitwise AND
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Specification: and_bitmask, and_bitmask_32
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### ANDS (immediate). Bitwise AND and set flags
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Specification: ands_bitmask, ands_bitmask_32
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### EOR (immediate). Bitwise exclusive OR
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Specification: eor_bitmask, eor_bitmask_32
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### ORR (immediate). Bitwise inclusive OR
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Specification: orr_bitmask, orr_bitmask_32
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### TST (immediate). TST Test bits
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Specification: tst_bitmask, tst_bitmask_32
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h3. Move (wide immediate)
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### MOVZ. Move wide with zero
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Specification: movz, movz_32
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### MOVN. Move wide with NOT
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Specification: movn, movn_32
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### MOVK. Move wide with keep
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Specification: movk, movk_32
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h3. Move (immediate)
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### MOV (wide immediate). Move (wide immediate)
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Specification: mov_wide_imm, mov_wide_imm_32
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### MOV (inverted wide immediate). Move (inverted wide immediate)
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Specification: mov_inv_wide_imm, mov_inv_wide_imm_32
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### MOV (bitmask immediate). Move (bitmask immediate)
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Specification: mov_bitmask, mov_bitmask_32
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h3. PC-relative address calculation
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### ADRP. Compute address of 4KB page at a PC-relative offset
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Specification: adrp
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### ADR. Compute address of label at a PC-relative offset.
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Specification: adr
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h3. Extract register
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### EXTR. Extract register from pair
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Specification: extr, extr_32
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h2. Data processing - register
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h3. Arithmetic (shifted register)
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### ADD (shifted register). Add
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Specification: add_sh_reg, add_sh_reg_32
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### ADDS (shifted register). Add and set flags
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Specification: adds_sh_reg, adds_sh_reg_32
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### SUB (shifted register). Subtract
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Specification: sub_sh_reg, sub_sh_reg_32
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### SUBS (shifted register). Subtract and set flags
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Specification: subs_sh_reg, subs_sh_reg_32
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### CMN (shifted register). Compare negative
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Specification: cmn_sh_reg, cmn_sh_reg_32
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### CMP (shifted register). Compare
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Specification: cmp_sh_reg, cmp_sh_reg_32
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h3. Arithmetic (extending register)
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### ADD (extended register). Add
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Specification: add_ex_reg, add_ex_reg_32
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### ADDS (extended register). Add and set flags
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Specification: adds_ex_reg, adds_ex_reg_32
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### SUB (extended register). Subtract
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Specification: sub_ex_reg, sub_ex_reg_32
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### SUBS (extended register). Subtract and set flags
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Specification: subs_ex_reg, subs_ex_reg_32
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### CMN (extended register). Compare negative
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Specification: cmn_ex_reg, cmn_ex_reg_32
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### CMP (extended register). Compare
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Specification: cmp_ex_reg, cmp_ex_reg_32
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h3. Logical (shifted register)
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### AND (shifted register). Bitwise AND
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Specification: and_bitwise, and_bitwise_32
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### ANDS (shifted register). Bitwise AND and set flags
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Specification: ands_bitwise, ands_bitwise_32
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### BIC (shifted register). Bitwise bit clear
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Specification: bic_bitwise, bic_bitwise_32
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### BICS (shifted register). Bitwise bit clear and set flags
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Specification: bics_bitwise, bics_bitwise_32
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### EON (shifted register). Bitwise exclusive OR NOT
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Specification: eon_bitwise, eon_bitwise_32
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### EOR (shifted register). Bitwise exclusive OR
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Specification: eor_bitwise, eor_bitwise_32
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### ORR (shifted register). Bitwise inclusive OR
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Specification: orr_bitwise, orr_bitwise_32
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### MVN. Bitwise NOT
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Specification: mvn_bitwise, mvn_bitwise_32
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### ORN (shifted register). Bitwise inclusive OR NOT
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Specification: orn_bitwise, orn_bitwise_32
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### TST (shifted register). Test bits
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Specification: tst_bitwise, tst_bitwise_32
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h3. Move (register)
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###  MOV (register). Move register
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Specification: mov_reg, mov_reg_32
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### MOV (to/from SP). Move register to SP or move SP to register
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Specification: mov_sp, mov_sp_32
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[47]: madd
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[48]: madd_32
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[49]: msub
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[50]: msub_32
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[51]: mneg
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[52]: mneg_32
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[53]: mul
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[54]: mul_32
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[55]: smaddl
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[56]: smsubl
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[57]: smnegl
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[58]: smull
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[59]: smulh
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[60]: umaddl
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[61]: umsubl
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[62]: umnegl
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[63]: umull
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[64]: umulh
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[65]: sdiv
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[66]: sdiv_32
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[67]: udiv
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[68]: udiv_32
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[115]: b
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[116]: cbnz
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[117]: cbnz_32
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[118]: cbz
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[119]: cbz_32
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[120]: tbnz
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[121]: tbz
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[122]: b_imm
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[123]: bl
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[124]: blr
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[125]: br
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[126]: ret
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[127]: ldr_postindex
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[128]: str_postindex
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[129]: ldxr
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[130]: ldxr_32
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[131]: ldxrb_32
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[132]: ldxrh_32
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[133]: ldxp
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[134]: ldxp_32
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[135]: stxr
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[136]: stxr_32
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[137]: stxrb_32
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[138]: stxrh_32
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[139]: stxp
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[140]: stxp_32
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[141]: ldar
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[142]: ldar_32
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[143]: ldarb
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[144]: ldarh
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[145]: stlr
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[146]: stlr_32
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[147]: stlrb
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[148]: stlrh
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[149]: ldaxr
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[150]: ldaxr_32
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[151]: ldaxrb_32
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[152]: ldaxrh_32
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[153]: ldaxp
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[154]: ldaxp_32
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[155]: stlxr
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[156]: stlxr_32
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[157]: stlxrb_32
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[158]: stlxrh_32
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[159]: stlxp
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[160]: stlxp_32
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[161]: svc
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[162]: hvc
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[163]: smc
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[164]: eret
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[165]: brk
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[166]: hlt
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[167]: dcps1
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[168]: dcps2
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[169]: dcps3
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[170]: drps
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[171]: mrs
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[172]: msr
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[173]: msr_dc
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[174]: msr_ds
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[175]: msr_ss
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[176]: msr_uao
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[177]: sys
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[178]: sysl
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[179]: ic
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[180]: ic_reg
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[181]: dc
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[182]: at
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[183]: tlbi
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[184]: tlbi_reg
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[185]: hint
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[186]: nop
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[187]: yield_op
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[188]: wfe
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[189]: wfi
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[190]: sev
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[191]: sevl
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[192]: clrex
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[193]: dsb
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[194]: dmb
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[195]: isb
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[200]: psldr
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[201]: psldr32